公开(公告)号：US20110191731A1

公开(公告)日：2011-08-04

申请号：US12697058

申请日：2010-01-29

申请人： Robert Walker ,  Mahesh A. Iyer

发明人： Robert Walker ,  Mahesh A. Iyer

IPC分类号： G06F17/50

CPC分类号： G06F17/50

摘要： Some embodiments provide a system that facilitates the creation of a design in an electronic design automation (EDA) application. During operation, the system determines a processing order for processing a set of cells in the design. In some embodiments, the processing order can be a reverse-levelized processing order. Next, the system may select a cell for performing area recovery according to the processing order. The system may then tentatively perform an area-recovery operation on the selected cell. Next, the system may determine a zone around the selected cell. Next, the system may propagate arrival times within the zone to obtain updated slack values at endpoints of the zone. The system may compute one or more timing metrics at the endpoints. If the updated slack values do not degrade the timing metric(s) at the endpoints, the system may accept the area-recovery operation of the selected cell.

摘要翻译： 一些实施例提供了一种便于在电子设计自动化（EDA）应用中创建设计的系统。 在操作期间，系统确定用于处理设计中的一组单元的处理顺序。 在一些实施例中，处理顺序可以是反向级别化的处理顺序。 接下来，系统可以根据处理顺序选择用于执行区域恢复的单元。 然后，系统可以暂时对所选择的小区执行区域恢复操作。 接下来，系统可以确定所选择的单元周围的区域。 接下来，系统可以在区域内传播到达时间，以在该区域的端点处获得更新的松弛值。 系统可以计算端点处的一个或多个时序度量。 如果更新的松弛值不降低端点处的定时度量，则系统可以接受所选小区的区域恢复操作。

公开(公告)号：US20110185334A1

公开(公告)日：2011-07-28

申请号：US12695556

申请日：2010-01-28

申请人： Mahesh A. Iyer ,  Sudipto Kundu

发明人： Mahesh A. Iyer ,  Sudipto Kundu

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78

摘要： A leakage power optimization system optimizes leakage power of a circuit design which includes a set of logic gates. The system selects a leakage-power-reducing transformation for a logic gate, and determines a zone around the logic gate. This zone includes logic gates within a first predetermined number of levels in the logic gate's fan-out, the logic gate's fan-in, and a second predetermined number of levels in the logic gate's fan-in's fan-out. The system propagates arrival times within the zone to obtain updated slack values at endpoints of the zone. Then, in response to determining that the updated slack values at the endpoints of the zone do not degrade one or more circuit timing metrics, the system applies the leakage-power-reducing transformation to the logic gate.

摘要翻译： 泄漏功率优化系统优化包括一组逻辑门的电路设计的漏电功率。 系统为逻辑门选择泄漏功率降低转换，并确定逻辑门周围的区域。 该区域包括在逻辑门的扇出，逻辑门的扇入中的第一预定数量级内的逻辑门和逻辑门的扇出扇出中的第二预定数量的级。 系统传播区域内的到达时间，以在区域的端点获得更新的松弛值。 然后，响应于确定区域端点处的更新的松弛值不降低一个或多个电路定时度量，系统将泄漏功率降低变换应用于逻辑门。

公开(公告)号：US07853915B2

公开(公告)日：2010-12-14

申请号：US12145405

申请日：2008-06-24

申请人： Prashant Saxena ,  Vishal Khandelwal ,  Changge Qiao ,  Pei-Hsin Ho ,  Jing C. Lin ,  Mahesh A. Iyer

发明人： Prashant Saxena ,  Vishal Khandelwal ,  Changge Qiao ,  Pei-Hsin Ho ,  Jing C. Lin ,  Mahesh A. Iyer

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.

摘要翻译： 提供持久性驱动的优化技术，其中可以基于不可预测性和可能的​​结果影响质量对网进行排名。 该排名中的顶级网络可以路由并提取其寄生效用。 时间图可以用针对所选网络的基于路由的延迟和寄生效应进行反向注释。 在这一点上，可以使用针对所选网络的实际基于路由的延迟和寄生效应来运行综合，并且根据需要递增地更新其路由。 在一个实施例中，网可以在合成后重新排列。 最后，这些路由可以在剩余网络的后续全局路由中保留。

公开(公告)号：US20090319977A1

公开(公告)日：2009-12-24

申请号：US12145405

申请日：2008-06-24

申请人： Prashant Saxena ,  Vishal Khandelwal ,  Changge Qiao ,  Pei-Hsin Ho ,  Jing C. Lin ,  Mahesh A. Iyer

发明人： Prashant Saxena ,  Vishal Khandelwal ,  Changge Qiao ,  Pei-Hsin Ho ,  Jing C. Lin ,  Mahesh A. Iyer

IPC分类号： G06F17/50

CPC分类号： G06F17/5077

摘要： A persistence-driven optimization technique is provided in which nets can be ranked based on unpredictability and likely quality of result impact. The top nets in that ranking can be routed and their parasitics extracted. A timing graph can be back-annotated with route-based delays and parasitics for the selected nets. At this point, synthesis can be run using actual route-based delays and parasitics for the selected nets, with their routes being updated incrementally as needed. In one embodiment, the nets can be re-ranked after synthesis. Finally, these routes can be preserved across the subsequent global routing of the remaining nets.

摘要翻译： 提供持久性驱动的优化技术，其中可以基于不可预测性和可能的​​结果影响质量对网进行排名。 该排名中的顶级网络可以路由并提取其寄生效用。 时间图可以用针对所选网络的基于路由的延迟和寄生效应进行反向注释。 在这一点上，可以使用针对所选网络的实际基于路由的延迟和寄生效应来运行综合，其路由根据需要被递增地更新。 在一个实施例中，网可以在合成后重新排列。 最后，这些路由可以在剩余网络的后续全局路由中保留。

公开(公告)号：US06334205B1

公开(公告)日：2001-12-25

申请号：US09255538

申请日：1999-02-22

申请人： Mahesh A. Iyer ,  Leon Stok ,  Andrew J. Sullivan

发明人： Mahesh A. Iyer ,  Leon Stok ,  Andrew J. Sullivan

IPC分类号： G06F1750

CPC分类号： G06F17/505

摘要： A technology mapping method and device for mapping cost functions on directed acyclic graphs, using decoupled matching and covering and circumventing the memory explosion usually caused by this decoupling. Multiple matches are generated at the head of a wavefront process and embedded within the network. Covering is done at the tail of the wavefront to optimize one or more cost functions.

摘要翻译： 一种技术映射方法和设备，用于映射有向非循环图上的成本函数，使用去耦匹配并覆盖和规避通常由该解耦造成的内存爆炸。 在波前处理的头部生成多个匹配并嵌入到网络中。 覆盖在波前的尾部完成，以优化一个或多个成本函数。

公开(公告)号：US5566187A

公开(公告)日：1996-10-15

申请号：US306088

申请日：1994-09-14

申请人： Miron Abramovici ,  Mahesh A. Iyer

发明人： Miron Abramovici ,  Mahesh A. Iyer

IPC分类号： G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F11/22 ,  G06F17/50 ,  G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318371 ,  G01R31/318342 ,  G01R31/318586

摘要： A method of identifying untestable faults in a logic circuit. A lead in the circuit is selected and the circuit is analyzed to determine which faults would be untestable if the selected circuit lead were unable to assume a logic 0 and which faults would be untestable if the selected circuit lead were unable to assume a logic 1. Faults that would be untestable in both (hypothetical) cases are identified as untestable faults. Faults which would be untestable if the selected lead were unable to assume a given value may be determined based on an implication procedure. The implication procedure comprises the forward propagation of uncontrollability indicators and the backward propagation of unobservability indicators. An uncontrollability indicator for the given value is assigned to the selected circuit lead and propagated forward through the circuit according to a set of well-defined propagation rules. In addition, unobservability indicators are generated in the circuit based on the propagation of uncontrollability indicators. These unobservability indicators are then propagated backward through the circuit. The (hypothetically) untestable faults are then determined based on the resultant indicators and their corresponding circuit leads. Untestable faults may be identified in a sequential circuit by generating an equivalent combinational iterative array circuit model for a fixed number of time frames. Faults that would be untestable in both (hypothetical) cases and which are located in the last (i.e., latest-in-time) time frame are identified as untestable faults.

摘要翻译： 一种识别逻辑电路中不可测试故障的方法。 选择电路中的引线，并分析电路，以确定如果所选电路引线不能承担逻辑0，哪些故障将不可测，如果所选电路引线不能采用逻辑1，哪些故障将不可测。 在两种（假设）情况下都是不可测试的故障被认定为不可测试的故障。 如果所选择的引线不能承担给定值，那么根据暗示过程可以确定不可测的故障。 暗示过程包括不可控指标的向前传播和不可观察指标的反向传播。 给定值的不可控性指示符被分配给所选择的电路引线，并根据一组明确的传播规则向前传播通过电路。 此外，基于不可控指标的传播，在电路中产生不可观察性指标。 然后，这些不可观察性指示器通过电路向后传播。 然后，根据所得到的指标及其对应的电路线确定（假设）不可测试的故障。 可以通过生成用于固定数量的时间帧的等效组合迭代阵列电路模型来在顺序电路中识别不可靠的故障。 在两个（假设）情况下，哪些位于最后（即时间上最晚的）时间框架内的故障将被认为是不可测试的故障。