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    ELECTRICALLY FORMED MEMORY ARRAY
    41.
    发明申请
    ELECTRICALLY FORMED MEMORY ARRAY 有权

    公开(公告)号：US20220190032A1

    公开(公告)日：2022-06-16

    申请号：US17122464

    申请日：2020-12-15

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00

    Abstract: The present disclosure includes electrically formed memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a first plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, a storage element material formed around each respective one of the first plurality of conductive extensions, a second plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a plurality of single element materials formed around each respective one of the second plurality of conductive extensions.

    PROGRAMMING ENHANCEMENT IN SELF-SELECTING MEMORY
    42.
    发明申请
    PROGRAMMING ENHANCEMENT IN SELF-SELECTING MEMORY 有权

    公开(公告)号：US20220172779A1

    公开(公告)日：2022-06-02

    申请号：US17544679

    申请日：2021-12-07

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano ,  Innocenzo Tortorelli ,  Fabio Pellizzer

    IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.

    TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE
    43.
    发明申请
    TECHNIQUES TO ACCESS A SELF-SELECTING MEMORY DEVICE 有权

    公开(公告)号：US20220115068A1

    公开(公告)日：2022-04-14

    申请号：US17499290

    申请日：2021-10-12

    Applicant: Micron Technology, Inc

    Inventor： Innocenzo Tortorelli ,  Andrea Redaelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Mario Allegra ,  Paolo Fantini

    IPC: G11C13/00 ,  H01L27/24 ,  G11C11/56 ,  H01L45/00

    Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

    Memory for embedded applications
    45.
    发明授权
    Memory for embedded applications 有权

    公开(公告)号：US11205681B2

    公开(公告)日：2021-12-21

    申请号：US17108795

    申请日：2020-12-01

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli

    IPC: G11C16/04 ,  H01L27/24 ,  H01L45/00 ,  H01L27/108 ,  G11C5/02 ,  G11C13/00 ,  G11C11/408

    Abstract: Memory devices for embedded applications are described. A memory device may include an array of memory cells having a first area and configured to operate at a first voltage, and circuitry having a second area that at least partially overlaps the first area. The circuitry may be configured to operate at a second voltage lower than the first voltage. The circuitry maybe be further configured to access the array of memory cells using decoder circuitry configured to operate at the first voltage. The array of memory cells and the circuitry may be on a single substrate. The circuitry may include microcontroller circuitry, cryptographic controller circuitry, and/or memory controller circuitry. The memory cells may be self-selecting memory cells that each include a storage and selector element having a chalcogenide material. The memory cells may not include separate cell selector circuitry.

    SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS
    46.
    发明申请
    SELF-ALIGNED MEMORY DECKS IN CROSS-POINT MEMORY ARRAYS 有权

    公开(公告)号：US20210328142A1

    公开(公告)日：2021-10-21

    申请号：US17308444

    申请日：2021-05-05

    Applicant: Micron Technology, Inc.

    Inventor： Agostino Pirovano ,  Fabio Pellizzer ,  Anna Maria Conti ,  Andrea Redaelli ,  Innocenzo Tortorelli

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A multi-layer memory device with an array having multiple memory decks of self-selecting memory cells is provided in which N memory decks may be fabricated with N+1 mask operations. The multiple memory decks may be self-aligned and certain manufacturing operations may be performed for multiple memory decks at the same time. For example, patterning a bit line direction of a first memory deck and a word line direction in a second memory deck above the first memory deck may be performed in a single masking operation, and both decks may be etched in a same subsequent etching operation. Such techniques may provide efficient fabrication which may allow for enhanced throughput, additional capacity, and higher yield for fabrication facilities relative to processing techniques in which each memory deck is processed using two or more mask and etch operations per memory deck.

    Memory for embedded applications
    50.
    发明授权
    Memory for embedded applications 有权

    公开(公告)号：US10658427B2

    公开(公告)日：2020-05-19

    申请号：US16164141

    申请日：2018-10-18

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli

    IPC: G11C11/00 ,  H01L27/24 ,  H01L45/00 ,  H01L27/108 ,  G11C5/02 ,  G11C13/00 ,  G11C11/408

    Abstract: A memory device may include an array of memory cells having a first area and configured to operate at a first voltage, and circuitry having a second area that at least partially overlaps the first area. The circuitry may be configured to operate at a second voltage lower than the first voltage. The circuitry maybe be further configured to access the array of memory cells using decoder circuitry configured to operate at the first voltage. The array of memory cells and the circuitry may be on a single substrate. The circuitry may include microcontroller circuitry, cryptographic controller circuitry, and/or memory controller circuitry. The memory cells may be self-selecting memory cells that each include a storage and selector element having a chalcogenide material. The memory cells may not include separate cell selector circuitry.

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