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    Predictive data orchestration in multi-tier memory systems
    41.
    发明授权
    Predictive data orchestration in multi-tier memory systems 有权

    公开(公告)号：US11354056B2

    公开(公告)日：2022-06-07

    申请号：US16905834

    申请日：2020-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Samir Mittal ,  Anirban Ray ,  Gurpreet Anand

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0811 ,  G06F13/16 ,  G06N3/08

    Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

    Isolated performance domains in a memory system
    42.
    发明授权
    Isolated performance domains in a memory system 有权

    公开(公告)号：US11275696B2

    公开(公告)日：2022-03-15

    申请号：US16893757

    申请日：2020-06-05

    Applicant: Micron Technology, Inc.

    Inventor： Anirban Ray ,  Parag R. Maharana

    IPC: G06F12/1009 ,  G06F12/02 ,  G06F9/455 ,  G06F9/50 ,  G06F9/30

    Abstract: A computing system having memory components, including first memory and second memory. The computing system further includes a processing device, operatively coupled with the memory components, to: store a memory allocation value in association with a context of executing instructions; execute a set of instructions in the context; allocate, for execution of the set of instructions in the context, an amount of memory, including an amount of the first memory and an amount of the second memory; and access the amount of the second memory via the amount of the first memory during the execution of the set of instructions in the context.

    Remote Direct Memory Access in Multi-Tier Memory Systems
    43.
    发明申请
    Remote Direct Memory Access in Multi-Tier Memory Systems 有权

    公开(公告)号：US20210349638A1

    公开(公告)日：2021-11-11

    申请号：US17382200

    申请日：2021-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Parag R. Maharana ,  Anirban Ray ,  Gurpreet Anand ,  Samir Mittal

    IPC: G06F3/06 ,  H04L29/08 ,  G11C14/00 ,  G06F13/28 ,  G06F15/173 ,  G06F12/00

    Abstract: A memory system having memory components, a remote direct memory access (RDMA) network interface card (RNIC), and a host system, and configured to: allocate a page of virtual memory for an application; map the page of virtual memory to a page of physical memory in the memory components; instruct the RNIC to perform an RDMA operation; perform, during the RDMA operation, a data transfer between the page of physical memory in the plurality of memory components and a remote device that is connected via a computer network to the remote direct memory access network interface card; and at least for a duration of the data transfer, lock a mapping between the page of virtual memory and the page of physical memory in the memory components.

    MEMORY TIERING USING PCIe CONNECTED FAR MEMORY
    45.
    发明申请
    MEMORY TIERING USING PCIe CONNECTED FAR MEMORY 有权

    公开(公告)号：US20210049101A1

    公开(公告)日：2021-02-18

    申请号：US16539139

    申请日：2019-08-13

    Applicant: Micron Technology, Inc.

    Inventor： Anirban Ray ,  Paul Stonelake ,  Samir Mittal ,  Gurpreet Anand

    IPC: G06F12/0868 ,  G06F13/28 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

    Abstract: A processing device in a host system monitors a data temperature of a plurality of memory pages stored in a host-addressable region of a cache memory component operatively coupled with the host system. The processing device determines that a first memory page of the plurality of memory pages satisfies a first threshold criterion pertaining to the data temperature of the first memory page and sends a first migration command indicating the first memory page to a direct memory access (DMA) engine executing on a memory-mapped storage component operatively coupled with the cache memory component and with the memory-mapped storage component via a peripheral component interconnect express (PCIe) bus. The first migration command causes the DMA engine to initiate a first DMA transfer of the first memory page from the cache memory component to a host-addressable region of the memory-mapped storage component.

    Predictive Data Orchestration in Multi-Tier Memory Systems
    46.
    发明申请
    Predictive Data Orchestration in Multi-Tier Memory Systems 审中-公开

    公开(公告)号：US20200319813A1

    公开(公告)日：2020-10-08

    申请号：US16905834

    申请日：2020-06-18

    Applicant: Micron Technology, Inc.

    Inventor： Samir Mittal ,  Anirban Ray ,  Gurpreet Anand

    IPC: G06F3/06 ,  G06F12/0811 ,  G06F13/16 ,  G06N3/08

    Abstract: A computing system having memory components of different tiers. The computing system further includes a controller, operatively coupled between a processing device and the memory components, to: receive from the processing device first data access requests that cause first data movements across the tiers in the memory components; service the first data access requests after the first data movements; predict, by applying data usage information received from the processing device in a prediction model trained via machine learning, second data movements across the tiers in the memory components; and perform the second data movements before receiving second data access requests, where the second data movements reduce third data movements across the tiers caused by the second data access requests.

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