公开(公告)号：US11662935B2

公开(公告)日：2023-05-30

申请号：US17400935

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Luigi Esposito ,  Alberto Sassara ,  Paolo Papa ,  Massimo Iaculo

IPC: G06F3/06

CPC classification number: G06F3/0649 ,  G06F3/0604 ,  G06F3/0646 ,  G06F3/0679

Abstract: Methods, systems, and devices for improved data management for memory are described. An apparatus may include a memory array including one or more blocks of memory cells. Data read from a block of memory cells may be written to a buffer, to support providing the data to a host system or modification of the data by the host system. If a quantity of read commands performed at the block of memory cells satisfies a threshold, the data may be written from the buffer to a different block of memory cells, rather than the block from which the data was previously read.

公开(公告)号：US11474865B2

公开(公告)日：2022-10-18

申请号：US16549218

申请日：2019-08-23

Applicant: Micron Technology, Inc.

Inventor： Angelo Della Monica ,  Paolo Papa ,  Carminantonio Manganelli ,  Massimo Iaculo

IPC: G06F9/50 ,  G06F12/1009 ,  G06F3/06

Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.

公开(公告)号：US20220261153A1

公开(公告)日：2022-08-18

申请号：US17580296

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Paolo Papa ,  Luigi Esposito ,  Massimo Iaculo ,  Giuseppe D'Eliseo ,  Alberto Sassara ,  Carminantonio Manganelli ,  Salvatore Del Prete

IPC: G06F3/06 ,  G06F12/06

Abstract: Methods, systems, and devices for data relocation operation techniques are described. A memory system may include blocks of memory cells, for example, within a non-volatile memory device of the memory system. The memory system may identify a command to perform a data relocation operation associated with a block of memory cells and may select between a first procedure and a second procedure for performing the data relocation operation. The memory system may select between the first procedure and the second procedure based on whether one or more parameters associated with the data relocation operation satisfy a threshold. For example, the memory system may select the first procedure if the one or more parameters satisfy the threshold and may select the second procedure if the one or more parameters do not satisfy the threshold. The memory system may perform the data relocation operation using the selected procedure.

公开(公告)号：US20210383872A1

公开(公告)日：2021-12-09

申请号：US17409413

申请日：2021-08-23

Applicant: Micron Technology, Inc.

Inventor： Paolo Papa ,  Luigi Esposito ,  Massimo Iaculo ,  Eric Kwok Fung Yuen ,  Gerard J. Perdaems

IPC: G11C16/10 ,  G06F3/06 ,  G06F11/07

Abstract: Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit, The memory controller may also store an indication that the first storage sub-unit is invalid.

公开(公告)号：US11106521B2

公开(公告)日：2021-08-31

申请号：US16544269

申请日：2019-08-19

Applicant: Micron Technology, Inc.

Inventor： Luigi Esposito ,  Paolo Papa ,  Massimo Iaculo ,  Erika Morvillo

IPC: G06F11/07

Abstract: Devices and techniques for fatal error logging in a memory device are described herein. For example a read request can be received for a component of the memory device. A fatal error indication of an error that prevents correct execution of read request can be detected. Diagnostic information for the failure indication can be collected. A response to the read request can then be made with a portion of the diagnostic information as payload instead of the user data that would have occupied the payload had the read succeeded. Metadata in the response can be used to communicate an error code.

公开(公告)号：US20210182207A1

公开(公告)日：2021-06-17

申请号：US16713552

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Giuseppe D`Eliseo ,  Carminantonio Manganelli ,  Paolo Papa ,  Yoav Weinberg ,  Giuseppe Ferrari ,  Massimo Laculo ,  Lalla Fatima Drissi

IPC: G06F12/1009

Abstract: In one approach, a computer storage device has one or more pivot tables and corresponding bit maps stored in volatile memory. The storage device has non-volatile storage media that stores data for a host device. The pivot tables and bit maps are used to determine physical addresses of the non-volatile storage media for logical addresses received in commands from the host device that are determined to be within a sequential address range (e.g., LBAs that are part of a prior sequential write operation by the host device). When a command is received by the storage device that includes a logical address within the sequential address range, then one of the pivot tables and its corresponding bit map are used to determine the physical address of the non-volatile storage media that corresponds to the logical address.

公开(公告)号：US10983918B2

公开(公告)日：2021-04-20

申请号：US16294427

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Carminantonio Manganelli ,  Yoav Weinberg ,  Alberto Sassara ,  Paolo Papa ,  Luigi Esposito ,  Giuseppe D'Eliseo ,  Angelo Della Monica ,  Massimo Iaculo

IPC: G06F12/1009

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.

公开(公告)号：US20210074343A1

公开(公告)日：2021-03-11

申请号：US17099347

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Marco Di Pasqua ,  Paolo Papa

IPC: G11C8/00 ,  G11C29/00 ,  G06F11/07 ,  G06F12/02

Abstract: A processing device of a system receives a request to access a selected sector in a memory component. The selected sector is associated with a sector number. The processing device determines a virtual block corresponding to the selected sector. The virtual block is associated with a misalignment factor and a misalignment counter. The processing device determines if the misalignment counter satisfies a threshold criterion. In response to the misalignment counter satisfying the threshold criterion, the processing device generates an updated sector number by shifting the sector number by the misalignment factor and performs the access to the selected sector using the updated sector number. In response to the misalignment counter not satisfying the threshold criterion, the processing device updates the misalignment counter and performs the access to the selected sector using the sector number.

公开(公告)号：US20200210344A1

公开(公告)日：2020-07-02

申请号：US16294427

申请日：2019-03-06

Applicant: Micron Technology, Inc.

Inventor： Carminantonio Manganelli ,  Yoav Weinberg ,  Alberto Sassara ,  Paolo Papa ,  Luigi Esposito ,  Giuseppe D'Eliseo ,  Angelo Della Monica ,  Massimo Iaculo

IPC: G06F12/1009

Abstract: A variety of applications can include systems and methods that utilize a hybrid logical to physical (L2P) caching scheme. A L2P cache and a L2P changelog in a storage device can be controlled for use in write and read operations of a memory system. A page pointer table in the L2P cache can be accessed, for performance of a write operation in the memory system, to obtain a specific physical address mapped to a specified logical block address from a host, where the access is based on the page pointer table loaded into the L2P cache from the L2P changelog. The L2P cache area can be progressively configured with the most frequently accessed page pointer tables in the L2P changelog in the latest host accesses.