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    Adaptive block mapping
    3.
    发明授权
    Adaptive block mapping 有权

    公开(公告)号：US11922069B2

    公开(公告)日：2024-03-05

    申请号：US17750131

    申请日：2022-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Alberto Sassara ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Luigi Esposito ,  Paolo Papa ,  Salvatore Del Prete ,  Xiangang Luo ,  Xiaolai Zhu

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

    Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

    ALLOCATION SCHEMA FOR A SCALABLE MEMORY AREA
    4.
    发明申请
    ALLOCATION SCHEMA FOR A SCALABLE MEMORY AREA 有权

    公开(公告)号：US20230033903A1

    公开(公告)日：2023-02-02

    申请号：US17962236

    申请日：2022-10-07

    Applicant: Micron Technology, Inc.

    Inventor： Angelo Della Monica ,  Paolo Papa ,  Carminantonio Manganelli ,  Massimo Laculo

    IPC: G06F9/50 ,  G06F12/1009 ,  G06F3/06

    Abstract: A variety of applications can include systems and methods that control a memory size of a changelog in a storage device, where the changelog is implemented to correlate virtual page addresses to physical addresses in one or more memory devices. The memory size can be controlled by an allocation schema for a scalable memory area for the changelog in the storage device. The allocation schema can include using bitmaps, lists linked to the bitmaps, and a counter to count bits asserted in the bitmaps such that the allocation of memory space in the storage device can depend on usage rather than allocating a large memory space for all possible correlations of virtual page addresses to physical addresses.

    Log data storage for flash memory
    6.
    发明授权
    Log data storage for flash memory 有权

    公开(公告)号：US11100996B2

    公开(公告)日：2021-08-24

    申请号：US15690889

    申请日：2017-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Papa ,  Luigi Esposito ,  Massimo Iaculo ,  Eric Kwok Fung Yuen ,  Gerard J. Perdaems

    IPC: G06F12/00 ,  G11C16/10 ,  G06F3/06 ,  G06F11/07 ,  G11C16/04

    Abstract: Devices and techniques for managing flash memory are disclosed herein. A memory controller may receive a first program request comprising first host data to be written to the flash memory. The flash memory may comprise a number of storage units with each storage unit comprising a number of storage sub-units. If the first host data is less than a remainder threshold, the memory controller may generate a first program data unit comprising the first host data and first log data describing the flash memory. The memory controller may program the program data unit to the first storage unit of the flash memory, where the first log data is written to a first storage sub-unit of the number of storage sub-unit. The memory controller may also store an indication that the first storage sub-unit is invalid.

    ADAPTIVE BLOCK MAPPING
    7.
    发明公开
    ADAPTIVE BLOCK MAPPING 审中-公开

    公开(公告)号：US20240272832A1

    公开(公告)日：2024-08-15

    申请号：US18586207

    申请日：2024-02-23

    Applicant: Micron Technology, Inc.

    Inventor： Alberto Sassara ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Luigi Esposito ,  Paolo Papa ,  Salvatore Del Prete ,  Xiangang Luo ,  Xiaolai Zhu

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

    Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

    DYNAMIC WEAR LEVELING TECHNIQUES
    8.
    发明公开
    DYNAMIC WEAR LEVELING TECHNIQUES 审中-公开

    公开(公告)号：US20240069741A1

    公开(公告)日：2024-02-29

    申请号：US17899341

    申请日：2022-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Luigi Esposito ,  Paolo Papa

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0292 ,  G06F2212/1036

    Abstract: Methods, systems, and devices for dynamic wear leveling techniques are described. A memory system may determine a type of data associated with data to be written to a block of the memory system. The memory system may determine the type of data based on a value of a counter associated with a segment of a mapping of the memory system that includes a logical address of the data. Additionally, or alternatively, the memory system may determine the type of data based on determining a quantity of invalid data in a set of recently selected (e.g., opened) blocks of the memory system. The memory system may select the block for storing the data based on the type of data and a quantity of times that the block has been erased and write the data to the selected block.

    ADAPTIVE BLOCK MAPPING
    9.
    发明公开
    ADAPTIVE BLOCK MAPPING 审中-公开

    公开(公告)号：US20230376245A1

    公开(公告)日：2023-11-23

    申请号：US17750131

    申请日：2022-05-20

    Applicant: Micron Technology, Inc.

    Inventor： Alberto Sassara ,  Giuseppe D'Eliseo ,  Lalla Fatima Drissi ,  Luigi Esposito ,  Paolo Papa ,  Salvatore Del Prete ,  Xiangang Luo ,  Xiaolai Zhu

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679

    Abstract: Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

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