公开(公告)号：US07332949B2

公开(公告)日：2008-02-19

申请号：US11367535

申请日：2006-03-03

申请人： Min-Su Kim

发明人： Min-Su Kim

IPC分类号： H03K3/289

CPC分类号： G01R31/318541 ,  H03K3/0375

摘要： Provided is a multi-threshold CMOS (MTCMOS) flip-flop for latching a data input signal in response to a clock signal and converting the latched signal to a data output signal. The flip-flop includes: a latch unit receiving the data input signal in a normal mode, latching the data input signal based on pulse signals and internal clock signals, transferring the latched data to an output terminal of the latch unit, outputting the transferred data as the data output signal, and performing a scan function by latching a scan signal; a pulse generator generating the pulse signals based on the clock signal and a scan enable signal, the pulse signals including a pulse signal and an inverted pulse signal; and a scan and retention latch unit generating the internal clock signals based on the clock signal and the scan enable signal, the internal clock signals including an internal clock signal and an inverted internal clock signal, storing data last input to the latch unit during the normal mode in a sleep mode in response to a control signal for controlling the sleep mode and the normal mode, performing a data retention function by transferring the stored data to the latch unit when the flip-flop returns to the normal mode from the sleep mode, performing the scan function by latching the scan signal, and transferring the scan signal to the latch unit, wherein the latch unit is connected to the scan and retention latch unit via a signal transfer line.

摘要翻译： 提供了一种多阈值CMOS（MTCMOS）触发器，用于响应于时钟信号锁存数据输入信号，并将锁存的信号转换为数据输出信号。 触发器包括：锁存单元，以正常模式接收数据输入信号，基于脉冲信号和内部时钟信号锁存数据输入信号，将锁存数据传送到锁存单元的输出端，输出传送数据 作为数据输出信号，并通过锁存扫描信号执行扫描功能; 脉冲发生器，其基于所述时钟信号和扫描使能信号产生所述脉冲信号，所述脉冲信号包括脉冲信号和反相脉冲信号; 以及扫描和保持锁存单元，其基于时钟信号和扫描使能信号产生内部时钟信号，内部时钟信号包括内部时钟信号和反相内部时钟信号，在正常期间将最后输入到锁存单元的数据存储 响应于用于控制睡眠模式和正常模式的控制信号而处于休眠模式的模式，当触发器从睡眠模式返回到正常模式时，通过将所存储的数据传送到锁存单元来执行数据保持功能， 通过锁定扫描信号执行扫描功能，并将扫描信号传送到锁存单元，其中锁存单元经由信号传输线连接到扫描和保持锁存单元。

公开(公告)号：US20070235815A1

公开(公告)日：2007-10-11

申请号：US11727936

申请日：2007-03-29

申请人： Min-Su Kim

发明人： Min-Su Kim

IPC分类号： H01L29/94

CPC分类号： H01L27/092 ,  H01L27/0207

摘要： Provided is a complementary metal oxide semiconductor (CMOS) inverter layout for increasing an effective channel length. The CMOS inverter layout may include first and second conductive MOS transistors respectively formed in first and second active regions, metal lines electrically connecting the first and second conductive MOS transistors, and one or more gate electrodes electrically connecting the gates of the first and second conductive MOS transistors. The widths of one or more gate electrodes may be set to a reduced and/or minimum feature size to reduce and/or minimize a process variation and a layout area of the CMOS inverter. Also, the first and second conductive MOS transistors may be connected in series via the metal lines to increase an effective channel length, thereby realizing a layout of the CMOS inverter having a longer delay than a conventional CMOS inverter.

摘要翻译： 提供了用于增加有效沟道长度的互补金属氧化物半导体（CMOS）逆变器布局。 CMOS反相器布局可以包括分别形成在第一和第二有源区域中的第一和第二导电MOS晶体管，电连接第一和第二导电MOS晶体管的金属线以及电连接第一和第二导电MOS的栅极的一个或多个栅电极 晶体管。 可以将一个或多个栅电极的宽度设置为减小和/或最小特征尺寸，以减少和/或最小化CMOS反相器的工艺变化和布局面积。 此外，第一和第二导电MOS晶体管可以经由金属线串联连接以增加有效沟道长度，从而实现具有比常规CMOS反相器更长的延迟的CMOS反相器的布局。

公开(公告)号：US20070075762A1

公开(公告)日：2007-04-05

申请号：US11635016

申请日：2006-12-07

申请人： Min-Su Kim

发明人： Min-Su Kim

IPC分类号： H03K3/00

CPC分类号： H03K5/151 ,  H03K3/037 ,  H03K5/135 ,  H03K5/1534

摘要： A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse-signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

摘要翻译： 基于脉冲的触发器，其锁存数据输入信号，以响应于时钟信号将数据输入信号转换成数据输出信号。 基于脉冲的触发器包括响应于第一时钟脉冲信号和第二时钟脉冲信号而锁存数据输入信号的锁存器和包括与非门，可变延迟和第一反相器的脉冲发生器，所述脉冲 发生器接收时钟信号以产生第一时钟脉冲信号和第二时钟脉冲信号。 NAND门接收时钟信号和可变延迟的输出信号，并输出第二时钟脉冲信号。 第一反相器接收第一时钟脉冲信号并输出​​第二时钟脉冲信号。 可变延迟接收时钟信号和第二时钟脉冲，并且可变延迟的输出信号反馈到NAND门。

公开(公告)号：US20070075761A1

公开(公告)日：2007-04-05

申请号：US11635012

申请日：2006-12-07

申请人： Min-Su Kim

发明人： Min-Su Kim

IPC分类号： H03K3/00

CPC分类号： H03K5/151 ,  H03K3/037 ,  H03K5/135 ,  H03K5/1534

摘要： A pulse-based flip-flop that latches a data input signal to convert the data input signal into a data output signal in response to a clock signal. The pulse-based flip-flop comprises a latch that latches the data input signal in response to a first clock pulse signal and a second clock pulse signal and a pulse generator including a NAND gate, a variable delay, and a first inverter, the pulse generator receives the clock signal to generate the first clock pulse signal and the second clock pulse signal. The NAND gate receives the clock signal and an output signal of the variable delay and outputs the second clock pulse signal. The first inverter receives the first clock pulse signal and outputs the second clock pulse signal. The variable delay receives the clock signal and the second clock pulse, and an output signal of the variable delay feeds back to the NAND gate.

摘要翻译： 基于脉冲的触发器，其锁存数据输入信号，以响应于时钟信号将数据输入信号转换成数据输出信号。 基于脉冲的触发器包括响应于第一时钟脉冲信号和第二时钟脉冲信号而锁存数据输入信号的锁存器和包括与非门，可变延迟和第一反相器的脉冲发生器，所述脉冲 发生器接收时钟信号以产生第一时钟脉冲信号和第二时钟脉冲信号。 NAND门接收时钟信号和可变延迟的输出信号，并输出第二时钟脉冲信号。 第一反相器接收第一时钟脉冲信号并输出​​第二时钟脉冲信号。 可变延迟接收时钟信号和第二时钟脉冲，可变延迟的输出信号反馈到NAND门。

公开(公告)号：US07154319B2

公开(公告)日：2006-12-26

申请号：US11064892

申请日：2005-02-24

申请人： Min-Su Kim

发明人： Min-Su Kim

IPC分类号： H03K3/12 ,  H03K3/289

CPC分类号： H03K3/0372 ,  H03K3/356121

摘要： A high-speed gated flip-flop includes a latch configured to generate a data output signal (Q) in response to a data input signal (D) and a pair of true and complementary clock pulses (GCP,GCPB). These clock pulses are provided by a clock generator responsive to a periodic clock signal (CK). A control circuit is also provided. The control circuit is coupled to a feedback node (ND2) in the pulse generator. The control circuit configured to selectively enable the pulse generator in response to an enable signal (/EN). The pulse generator is configured so that an active transition of the true clock pulse (GCP) is fed back to the feedback node (ND2) in a manner that resets the pulse generator and terminates the true and complementary clock pulses in-sync with the active (e.g., low-to-high) transition of the true clock pulse (GCP).

公开(公告)号：US20060244502A1

公开(公告)日：2006-11-02

申请号：US11364003

申请日：2006-03-01

申请人： Min-Su Kim

发明人： Min-Su Kim

IPC分类号： H03K3/356

CPC分类号： G11C7/065 ,  H03K3/356139

摘要： The sense amplifier-based flip-flop circuit includes a pulse generator and a sense amplifier. The pulse generator is configured to generate a signal pulse in response to one of a first transition and a second transition of a clock signal. The sense amplifier is configured to sense differential input signals in response to the signal pulse and maintain the sensed differential input signals until a subsequent signal pulse is received.

摘要翻译： 基于感测放大器的触发器电路包括脉冲发生器和读出放大器。 脉冲发生器被配置为响应于时钟信号的第一转换和第二转换中的一个产生信号脉冲。 读出放大器被配置为响应于信号脉冲感测差分输入信号，并保持所感测到的差分输入信号，直到接收到后续的信号脉冲。

公开(公告)号：US20060197571A1

公开(公告)日：2006-09-07

申请号：US11367535

申请日：2006-03-03

申请人： Min-Su Kim

发明人： Min-Su Kim

IPC分类号： H03K3/037

CPC分类号： G01R31/318541 ,  H03K3/0375

摘要： Provided is a multi-threshold CMOS (MTCMOS) flip-flop for latching a data input signal in response to a clock signal and converting the latched signal to a data output signal. The flip-flop includes: a latch unit receiving the data input signal in a normal mode, latching the data input signal based on pulse signals and internal clock signals, transferring the latched data to an output terminal of the latch unit, outputting the transferred data as the data output signal, and performing a scan function by latching a scan signal; a pulse generator generating the pulse signals based on the clock signal and a scan enable signal, the pulse signals including a pulse signal and an inverted pulse signal; and a scan and retention latch unit generating the internal clock signals based on the clock signal and the scan enable signal, the internal clock signals including an internal clock signal and an inverted internal clock signal, storing data last input to the latch unit during the normal mode in a sleep mode in response to a control signal for controlling the sleep mode and the normal mode, performing a data retention function by transferring the stored data to the latch unit when the flip-flop returns to the normal mode from the sleep mode, performing the scan function by latching the scan signal, and transferring the scan signal to the latch unit, wherein the latch unit is connected to the scan and retention latch unit via a signal transfer line.

摘要翻译： 提供了一种多阈值CMOS（MTCMOS）触发器，用于响应于时钟信号锁存数据输入信号，并将锁存的信号转换为数据输出信号。 触发器包括：锁存单元，以正常模式接收数据输入信号，基于脉冲信号和内部时钟信号锁存数据输入信号，将锁存数据传送到锁存单元的输出端，输出传送数据 作为数据输出信号，并通过锁存扫描信号执行扫描功能; 脉冲发生器，其基于所述时钟信号和扫描使能信号产生所述脉冲信号，所述脉冲信号包括脉冲信号和反相脉冲信号; 以及扫描和保持锁存单元，其基于时钟信号和扫描使能信号产生内部时钟信号，内部时钟信号包括内部时钟信号和反相内部时钟信号，在正常期间将最后输入到锁存单元的数据存储 响应于用于控制睡眠模式和正常模式的控制信号而处于休眠模式的模式，当触发器从睡眠模式返回到正常模式时，通过将所存储的数据传送到锁存单元来执行数据保持功能， 通过锁定扫描信号执行扫描功能，并将扫描信号传送到锁存单元，其中锁存单元经由信号传输线连接到扫描和保持锁存单元。

公开(公告)号：US20060020458A1

公开(公告)日：2006-01-26

申请号：US11008687

申请日：2004-12-10

申请人： Young-Hun Kwon ,  Kun-Sang Lee ,  Sung-Il Yang ,  Sung-Wook Chang ,  Jung-Pa Seo ,  Min-Su Kim ,  In-Chan Baek

发明人： Young-Hun Kwon ,  Kun-Sang Lee ,  Sung-Il Yang ,  Sung-Wook Chang ,  Jung-Pa Seo ,  Min-Su Kim ,  In-Chan Baek

IPC分类号： G10L17/00

CPC分类号： G10L17/02

摘要： Disclosed herein is a similar speaker recognition method and system using nonlinear analysis. The recognition method extracts a nonlinear feature of a sound signal through nonlinear analysis of the sound signal and combines the nonlinear feature with a linear feature such as spectrum. The method transforms sound data in a time domain into status vectors in a phase domain and uses a nonlinear time series analysis method capable of representing nonlinear features of the status vectors to extract nonlinear information of a sound. The method can overcome technical limitations of conventional linear algorithms. The recognition method can be applied to sound-related application systems other than speaker recognition systems.

摘要翻译： 这里公开的是使用非线性分析的类似的说话者识别方法和系统。 识别方法通过声音信号的非线性分析提取声音信号的非线性特征，并将非线性特征与光谱等线性特征相结合。 该方法将时域中的声音数据转换为相域中的状态向量，并使用能够表示状态向量的非线性特征的非线性时间序列分析方法来提取声音的非线性信息。 该方法可以克服传统线性算法的技术局限性。 识别方法可以应用于除扬声器识别系统之外的声音相关应用系统。

公开(公告)号：US20050253640A1

公开(公告)日：2005-11-17

申请号：US11128294

申请日：2005-05-13

申请人： Min-Su Kim

发明人： Min-Su Kim

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H03K3/037 ,  H03K3/289 ,  H03K3/356 ,  H03K19/096

CPC分类号： G01R31/318575 ,  G01R31/318552 ,  H03K3/0375

摘要： A control signal generator, latch circuit, flip-flop and method for controlling operations in the flip-flop may be configured so as to efficiently perform latching and scanning operations in the flip-flop. The control signal generator may generate at least two pulses based on a scan enable signal being received in a first state and on a received clock signal, and may generate at least two internal clock signals based on the received clock signal, and based on the scan enable signal being received in a second state. The latch circuit may latch a received input signal based on the at least two pulses and may latch a received scan input signal based on the at least two internal clock signals.

摘要翻译： 可以配置用于控制触发器中的操作的控制信号发生器，锁存电路，触发器和方法，以有效地执行触发器中的锁存和扫描操作。 控制信号发生器可以基于在第一状态和接收的时钟信号中接收到的扫描使能信号来生成至少两个脉冲，并且可以基于接收到的时钟信号，并且基于扫描来生成至少两个内部时钟信号 使能信号在第二状态下被接收。 锁存电路可以基于至少两个脉冲来锁存接收到的输入信号，并且可以基于至少两个内部时钟信号来锁存接收到的扫描输入信号。

公开(公告)号：US20050237097A1

公开(公告)日：2005-10-27

申请号：US11099592

申请日：2005-04-06

申请人： Min-Su Kim

发明人： Min-Su Kim

IPC分类号： G11C7/00 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356

CPC分类号： H03K3/012 ,  H03K3/356156

摘要： A latch and a data storage device including the latch are provided. The data storage device includes a pulse generator to produce a first control signal and a second control signal. The latch include: a first inverter to invert an input signal; a non-CMOS switch to selectively pass the inverted input signal output by the first inverter to a node; a second inverter to provide a first inverted version of a middle signal on the node; a first power supply to controllably raise a voltage of the middle signal according to the first inverted version of the middle signal; a second power supply to controllably lower a voltage of the middle signal according to the first inverted version of the middle signal and the second control signal, and a third inverter to provide, as an output signal, a second inverted version of the middle signal on the node.

摘要翻译： 提供了包括锁存器的锁存器和数据存储装置。 数据存储装置包括产生第一控制信号和第二控制信号的脉冲发生器。 锁存器包括：第一反相器，用于反相输入信号; 非CMOS开关，用于选择性地将由第一反相器输出的反相输入信号传递到节点; 第二逆变器，用于在所述节点上提供中间信号的第一反向版本; 第一电源，用于根据中间信号的第一反向版本可控地提高中间信号的电压; 第二电源，用于根据中间信号和第二控制信号的第一反向版本可控制地降低中间信号的电压;以及第三反相器，提供中间信号的第二反向版本作为输出信号 节点。