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    3D semiconductor device, structure and methods
    41.
    发明授权
    3D semiconductor device, structure and methods 有权

    公开(公告)号：US11502095B2

    公开(公告)日：2022-11-15

    申请号：US16649660

    申请日：2018-09-23

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist ,  Eli Lusky

    IPC: H01L27/11556 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538 ,  H01L23/66 ,  H01L27/11582

    Abstract: A 3D device, the device including: at least a first level including logic circuits; at least a second level including an array of memory cells; at least a third level including special circuits; and at least a fourth level including special connectivity structures, where the special connectivity structures include one of the following: a. waveguides, or b. differential signaling, or c. radio frequency transmission lines, or d. Surface Waves Interconnect (SWI) lines, and where the third level includes Radio Frequency (“RF”) circuits to drive the special connectivity structures, where the second level overlays the first level, where the third level overlays the second level, and where the fourth level overlays the third level.

    3D memory devices and structures with thinned single crystal substrates
    43.
    发明授权
    3D memory devices and structures with thinned single crystal substrates 有权

    公开(公告)号：US11329059B1

    公开(公告)日：2022-05-10

    申请号：US17567049

    申请日：2021-12-31

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H01L23/52 ,  H01L27/11556 ,  H01L27/11582 ,  G11C5/02

    Abstract: A semiconductor device, the device including: a first level overlaid by a first memory control level; a first memory level disposed on top of said first control level, where said first memory level includes a first thinned single crystal substrate; a second memory level, said second memory level disposed on top of said first memory level, where said second memory level includes a second thinned single crystal substrate, where said memory control level is bonded to said first memory level, and where said bonded includes oxide to oxide and conductor to conductor bonding.

    3D MEMORY DEVICE AND STRUCTURE
    45.
    发明申请
    3D MEMORY DEVICE AND STRUCTURE 有权

    公开(公告)号：US20220013485A1

    公开(公告)日：2022-01-13

    申请号：US17485504

    申请日：2021-09-27

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/544 ,  H01L25/00

    Abstract: A semiconductor device, the device including: a first level overlaid by a first memory level, where the first memory level includes a first thinned single crystal substrate; a second memory level, the second memory level disposed on top of the first memory level, where the second memory level includes a second thinned single crystal substrate; and a memory control level disposed on top of the second memory level, where the memory control level is bonded to the second memory level, and where the bonded includes oxide to oxide and conductor to conductor bonding.

    SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE
    46.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND STRUCTURE 有权

    公开(公告)号：US20210366921A1

    公开(公告)日：2021-11-25

    申请号：US17367385

    申请日：2021-07-04

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han

    IPC: H01L27/11556 ,  G11C5/02 ,  H01L27/11582 ,  H01L23/538

    Abstract: A 3D semiconductor device, the device including: a first level including first single crystal transistors; and a second level including second single crystal transistors, where the first level is overlaid by the second level, where a vertical distance from the first single crystal transistors to the second single crystal transistors is less than eight microns, where the second level includes a layer transferred and bonded level, where the bonded includes oxide to oxide bonds, where the first level includes a plurality of processors, and where the second level includes a plurality of memory cells.

    3D memory semiconductor devices and structures
    49.
    发明授权
    3D memory semiconductor devices and structures 有权

    公开(公告)号：US10892016B1

    公开(公告)日：2021-01-12

    申请号：US16836659

    申请日：2020-03-31

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11582

    Abstract: A method to operate a 3D semiconductor charge trap memory device, the method comprising; executing a memory set-up operation, wherein said memory set-up operation comprises a preload of a plurality of memory cells followed by a partial erase; and then executing a memory operation on said memory cells, wherein each memory cell of said plurality of memory cells comprises a charge trap layer, wherein said memory operation comprises first writing a first memory state by loading a charge into said charge trap layer, and then second writing a second memory state by removing said charge to a partially erased state. Various 3D devices, processing flows and methods are also disclosed.

    3D SEMICONDUCTOR DEVICE AND STRUCTURE
    50.
    发明申请
    3D SEMICONDUCTOR DEVICE AND STRUCTURE 审中-公开

    公开(公告)号：US20200176420A1

    公开(公告)日：2020-06-04

    申请号：US16558304

    申请日：2019-09-02

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/46 ,  H01L25/00

    Abstract: A 3D semiconductor device, the device including: a first level; a second level; and a third level, where the first level includes single crystal silicon and a plurality of logic circuits, where the second level is disposed directly above the first level and includes a first plurality of arrays of memory cells, where the third level is disposed directly above the second level and includes a plurality of RF circuits, and where a portion of interconnections between the plurality of logic circuits includes the RF circuits.

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