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公开(公告)号：US07366651B1
公开(公告)日：2008-04-29
申请号：US10388681
申请日：2003-03-14
IPC分类号： G06F9/455 , G06F9/44 , G06F9/06 , G06F9/00 , G06F17/50 , G06F17/00 , G01R31/28 , G01R35/00 , G06F11/00
CPC分类号： G06F17/5022 , G06F2217/86
摘要： Method and apparatus for interfacing between a high-level modeling system and a hardware description language (HDL) co-simulation engine. A plurality of HDL co-simulation engine libraries are queried as to the capabilities of the engines. A co-simulation engine is selected based on the capabilities, and an instance of the engine is created. The selected co-simulation engine is configured, input logic vectors are provided to the selected HDL co-simulation engine, and the co-simulation engine is executed accordingly.
摘要翻译： 用于在高级建模系统和硬件描述语言（HDL）协同仿真引擎之间进行接口的方法和装置。 关于发动机性能的多个HDL协同仿真引擎库被查询。 基于能力选择协同仿真引擎，并且创建引擎的实例。 配置所选择的协同仿真引擎，将输入逻辑向量提供给所选择的HDL协同仿真引擎，并且相应地执行协同仿真引擎。
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公开(公告)号：US07287178B1
公开(公告)日：2007-10-23
申请号：US11095282
申请日：2005-03-31
IPC分类号： G06F1/12
CPC分类号： G06F17/5045 , G06F2217/62
摘要： Methods are provided for creating an electronic system. A subsystem hierarchy is created that includes a plurality of subsystems for the electronic system. Certain subsystems are associated with a clock domain including a first subsystem associated with one clock domain and a second subsystem associated with another clock domain. A first stub component is instantiated in the first subsystem and a second stub component is instantiated in the second subsystem. Each stub component is instantiated in a parent subsystem and is coupled to signals in the parent subsystem. Stub components are matched based on user-configurable data associated with each stub component. Each set of matching stub components is replaced with a synchronizer component selected based on type data associated with each stub component. The signals in the parent subsystem for the matched stub components are coupled to the selected synchronizer component.
摘要翻译： 提供了用于创建电子系统的方法。 创建包括用于电子系统的多个子系统的子系统层次结构。 某些子系统与包括与一个时钟域相关联的第一子系统和与另一个时钟域相关联的第二子系统的时钟域相关联。 在第一子系统中实例化第一存根分量，并在第二子系统中实例化第二存根分量。 每个存根组件在父子系统中实例化，并且耦合到父子系统中的信号。 存根组件根据与每个存根组件相关联的用户可配置数据进行匹配。 每组匹配的存根组件被替换为基于与每个存根组件相关联的类型数据选择的同步器组件。 用于匹配存根组件的父子系统中的信号耦合到所选择的同步器组件。
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43.发明授权Method of and apparatus for specifying clock domains in electronic circuit designs 有权电子电路设计中指定时钟域的方法和装置公开(公告)号：US07269811B1
公开(公告)日：2007-09-11
申请号：US10340005
申请日：2003-01-10
CPC分类号： G06F17/5045 , G06F2217/62
摘要： A method of specifying clock domains in electronic circuit designs in a system level design tool is disclosed. The method generally comprises steps of providing a design having a plurality of functional blocks; incorporating a clock tag block within the design; and setting a clock domain provided by the clock tag block for a functional block of the plurality of functional blocks. A design tool enabling the association of clock domains with functional blocks in a system is also disclosed. The design tool generally comprises a plurality of functional blocks; a clock tag block having a predetermined clock rate; and a user interface enabling the selection of the functional blocks and the clock tag block in a design. The clock tag block provides a clock rate for at least one functional block of the plurality of functional blocks.
摘要翻译： 公开了一种在系统级设计工具中指定电子电路设计中的时钟域的方法。 该方法通常包括提供具有多个功能块的设计的步骤; 在设计中加入时钟标签块; 以及设置由所述时钟标签块提供的用于所述多个功能块的功能块的时钟域。 还公开了一种使时钟域与系统中的功能块相关联的设计工具。 该设计工具通常包括多个功能块; 具有预定时钟频率的时钟标签块; 以及能够在设计中选择功能块和时钟标签块的用户界面。 时钟标签块为多个功能块中的至少一个功能块提供时钟速率。
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公开(公告)号：US07068071B1
公开(公告)日：2006-06-27
申请号：US10970962
申请日：2004-10-22
IPC分类号： H03K7/38
CPC分类号： H03K19/17736 , H03K19/17732 , H03K19/1774
摘要： An integrated circuit with overclocked embedded logic circuitry is described. In an example, a programmable logic device includes programmable logic blocks operable using a first clock signal having a first frequency. A dedicated logic circuit embedded within the programmable logic device is operable using a second clock signal synchronized with the first clock signal and having a second frequency, the second frequency being a multiple of the first frequency. An interface coupled between one or more of the programmable logic blocks and the dedicated logic circuit includes multiplexer circuitry to multiplex output signals produced by the one or more programmable logic blocks among input terminals of the dedicated logic circuit.
摘要翻译： 描述了具有超频嵌入式逻辑电路的集成电路。 在一个示例中，可编程逻辑器件包括可使用具有第一频率的第一时钟信号操作的可编程逻辑块。 嵌入在可编程逻辑器件内的专用逻辑电路使用与第一时钟信号同步并具有第二频率的第二时钟信号来工作，第二频率是第一频率的倍数。 耦合在一个或多个可编程逻辑块和专用逻辑电路之间的接口包括多路复用器电路，用于在专用逻辑电路的输入端之间复用由一个或多个可编程逻辑块产生的输出信号。
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45.发明授权Method and system for generating a circuit design including a peripheral component connected to a bus 有权用于产生包括连接到总线的外围组件的电路设计的方法和系统公开(公告)号：US06883147B1
公开(公告)日：2005-04-19
申请号：US10304471
申请日：2002-11-25
申请人： Jonathan B. Ballagh , Roger Brent Milne , Jeffrey D. Stroomer , Eric R. Keller , L. James Hwang , Philip B. James-Roxby
发明人： Jonathan B. Ballagh , Roger Brent Milne , Jeffrey D. Stroomer , Eric R. Keller , L. James Hwang , Philip B. James-Roxby
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/505
摘要： Method and system for generating an electronic circuit design. A first logic block is instantiated in the design in response to user input controls. The first logic block includes parameters that specify its interface requirements. Bus interface blocks, which are parameterizable to connect a logic block to a bus, are provided in a library. Bus interface blocks that connect the first logic block to the bus are instantiated in the design, and the bus interface blocks are parameterized in response to the requirements of, the first logic block. The bus interface blocks are connected to the first logic block in such a way that the first logic block is extended into a peripheral that can communicate with the bus.
摘要翻译： 用于生成电子电路设计的方法和系统。 响应于用户输入控件，第一个逻辑块在设计中实例化。 第一个逻辑块包括指定其接口要求的参数。 在库中提供了可以将逻辑块连接到总线的总线接口块。 在设计中实例化了将第一个逻辑块连接到总线的总线接口块，并根据第一个逻辑块的要求对总线接口块进行参数化。 总线接口块以这样的方式连接到第一逻辑块，使得第一逻辑块被扩展到可以与总线通信的外设。
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公开(公告)号：US09208174B1
公开(公告)日：2015-12-08
申请号：US11942484
申请日：2007-11-19
申请人： Jonathan B. Ballagh , Thomas E. Fischaber , Roger B. Milne , Krista M. Marks , Theodore J. Stroomer
发明人： Jonathan B. Ballagh , Thomas E. Fischaber , Roger B. Milne , Krista M. Marks , Theodore J. Stroomer
CPC分类号： G06F17/30268 , G06F17/30277 , G06F17/3028
摘要： Disclosed are various approaches for searching for electronic information. In one embodiment, a first plurality of objects is presenting for user selection. The first plurality of objects is a first subset of a second plurality of objects that is organized by a plurality of containment categories in a data structure. A plurality of associations is stored, and each association defines a relationship between one of, two different ones of the plurality of categories, or two objects in two different ones of the plurality of containment categories. In response to user selection of one of the first plurality of objects, a second subset of the second plurality of objects is selected. Selection of the objects in the second subset is in part a function of respective weighted relevance values for associations of the selected object to each of the second plurality of objects. The second subset of objects is output.
摘要翻译： 公开了用于搜索电子信息的各种方法。 在一个实施例中，呈现用于用户选择的第一多个对象。 第一多个对象是由数据结构中的多个容纳类别组织的第二多个对象的第一子集。 存储多个关联，并且每个关联定义多个类别中的一个，两个不同类别中的一个，或多个容纳类别中的两个不同类别中的两个对象之间的关系。 响应于用户选择第一多个对象之一，选择第二多个对象的第二子集。 第二子集中的对象的选择部分地是用于所选对象与第二多个对象中的每一个的关联的各个加权相关值的函数。 输出第二个对象子集。
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47.发明授权Method of abstracting a graphical object in a line art style suitable for printing and artwork-coloring 有权以适合于印刷和艺术品着色的线条艺术风格抽象图形对象的方法公开(公告)号：US08207969B1
公开(公告)日：2012-06-26
申请号：US11956467
申请日：2007-12-14
IPC分类号： G06T11/20
CPC分类号： G06T11/40 , G06T11/203
摘要： Various approaches are disclosed for generating an output graphical object from an input graphical object. In one approach, vector graphics data representing the input graphical object in a memory are stored. A first subset of the vector graphics components of the vectors graphics data to leave unchanged for the output graphical object, a second subset of vector graphics components to alter for the output object, and a third subset of vector graphics components to discard from the output object are determined. Each vector graphics component in the second subset is altered, and the first and altered second subsets of vector graphics components as the output graphical object.
摘要翻译： 公开了用于从输入图形对象生成输出图形对象的各种方法。 在一种方法中，存储表示存储器中的输入图形对象的矢量图形数据。 图形数据的矢量图形组件的第一子集，用于输出图形对象保持不变的向量图形组件的第二子集，用于输出对象改变的向量图形组件的第二子集，以及从输出对象中丢弃的矢量图形组件的第三子集 确定。 第二子集中的每个矢量图形组件被改变，并且矢量图形组件的第一个和改变的第二子集作为输出图形对象。
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48.发明授权公开(公告)号：US08082139B1
公开(公告)日：2011-12-20
申请号：US11729400
申请日：2007-03-27
IPC分类号： G06F17/50
CPC分类号： G06F17/5027 , G06F2217/86
摘要： Methods and systems for simulating an electronic system in a high level modeling system (HLMS). A design block and certain signals of the electronic system are selected. The selected signals include internal signals of the design block that are not ports of the design block. The electronic system is simulated in the HLMS, which includes a hardware-based co-simulation platform and a software-based co-simulation platform. A hardware realization of the design block is automatically generated and the design block is emulated in the hardware based co-simulation platform using the hardware realization of the design block. A sequence of values is displayed for the selected signals of the electronic system. During the simulation of the electronic system in the HLMS, the sequence of values for the internal signals of the design block and another sequence of values for the ports of the design block are transferred between the co-simulation platforms.
摘要翻译： 在高级建模系统（HLMS）中模拟电子系统的方法和系统。 选择电子系统的设计块和某些信号。 所选择的信号包括不是设计块端口的设计块的内部信号。 电子系统在HLMS中模拟，其中包括基于硬件的协同仿真平台和基于软件的协同仿真平台。 自动生成设计块的硬件实现，并使用设计块的硬件实现在基于硬件的协同仿真平台中仿真设计块。 为电子系统的选定信号显示一系列值。 在HLMS中的电子系统的仿真期间，设计块的内部信号的值序列和设计块的端口的另一个值序列在协同仿真平台之间传输。
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49.发明授权公开(公告)号：US07870522B1
公开(公告)日：2011-01-11
申请号：US12043284
申请日：2008-03-06
CPC分类号： G06F17/5009
摘要： A method communicates data with efficient conversion between representations in a high-level modeling system. The data is communicated from a first block in a first external format and the data is communicated to a second block in a second external format. The first block has a first internal representation of the data and the second block has a second internal representation of the data. The first internal representation is converted to the second internal representation without intermediate representation in the first and second external formats in response to different first and second external formats or different first and second internal representations. Conversion between the representations of the data is bypassed in response to like first and second external formats and like first and second internal representations. A signal instance is created that communicates the data between the blocks. Converters between data representations are installed in the signal instance on demand.
摘要翻译： 一种方法在高级建模系统中的表示之间有效地转换数据。 以第一外部格式从第一块传送数据，并以第二外部格式将数据传送到第二块。 第一块具有数据的第一内部表示，并且第二块具有数据的第二内部表示。 响应于不同的第一和第二外部格式或不同的第一和第二内部表示，第一内部表示被转换为第二内部表示而没有在第一和第二外部格式中的中间表示。 响应于类似的第一和第二外部格式以及像第一和第二内部表示一样绕过数据表示之间的转换。 创建一个信号实例来传达块之间的数据。 数据表示之间的转换器根据需要安装在信号实例中。
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50.发明授权公开(公告)号：US07366998B1
公开(公告)日：2008-04-29
申请号：US11268832
申请日：2005-11-08
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： A method communicates data with efficient conversion between representations in a high-level modeling system. The data is communicated from a first block in a first external format and the data is communicated to a second block in a second external format. The first block has a first internal representation of the data and the second block has a second internal representation of the data. The first internal representation is converted to the second internal representation without intermediate representation in the first and second external formats in response to different first and second external formats or different first and second internal representations. Conversion between the representations of the data is bypassed in response to like first and second external formats and like first and second internal representations. A signal instance is created that communicates the data between the blocks. Converters between data representations are installed in the signal instance on demand.
摘要翻译： 一种方法在高级建模系统中的表示之间有效地转换数据。 以第一外部格式从第一块传送数据，并以第二外部格式将数据传送到第二块。 第一块具有数据的第一内部表示，并且第二块具有数据的第二内部表示。 响应于不同的第一和第二外部格式或不同的第一和第二内部表示，第一内部表示被转换为第二内部表示而没有在第一和第二外部格式中的中间表示。 响应于类似的第一和第二外部格式以及像第一和第二内部表示一样绕过数据表示之间的转换。 创建一个信号实例来传达块之间的数据。 数据表示之间的转换器根据需要安装在信号实例中。
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