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公开(公告)号：US10804865B1
公开(公告)日：2020-10-13
申请号：US16729495
申请日：2019-12-30
发明人： Chieh-An Lin , Yen-Ru Kuo , Jhih-Siou Cheng , Ju-Lin Huang
摘要： A current integrator includes an operational amplifier, an integration capacitor and an offset cancelation capacitor. The operational amplifier includes a first input stage and a second input stage. The first input stage is coupled to an input terminal of the current integrator. The integration capacitor is coupled between the first input stage of the operational amplifier and an output terminal of the current integrator. The offset cancelation capacitor is coupled to the second input stage of the operational amplifier.
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公开(公告)号：US10789895B2
公开(公告)日：2020-09-29
申请号：US16009290
申请日：2018-06-15
发明人： Chih-Hsien Chou , Po-Yu Tseng , Jhih-Siou Cheng
IPC分类号： G09G3/36 , G09G3/3283 , H03F3/45
摘要： The differential difference amplifier circuit includes a differential input stage circuit, a loading stage circuit coupled to the differential input stage circuit, and an output stage circuit coupled to the loading stage circuit. The output stage circuit is configured to generate an output signal. The differential input stage circuit includes a first differential pair having a first transconductance and a second differential pair having a second transconductance. The first differential pair is biased by a first current source and receives a first input signal and the output signal. The second differential pair is biased by a second current source and receives a second input signal and the output signal. At least one of the first transconductance and the second transconductance is adjusted according to the image data.
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43.发明授权公开(公告)号：US10673391B2
公开(公告)日：2020-06-02
申请号：US16402349
申请日：2019-05-03
发明人： Chih-Wen Lu , Chih-Hsien Chou , Po-Yu Tseng , Jhih-Siou Cheng
摘要： An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.
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公开(公告)号：US20200020282A1
公开(公告)日：2020-01-16
申请号：US16512413
申请日：2019-07-16
发明人： Chih-Hsien Chou , Jhih-Siou Cheng , Jin-Yi Lin
IPC分类号： G09G3/3291
摘要： A source driver is configured to drive an organic light-emitting diode (OLED) display panel. The source driver includes a sensing circuit and an operational amplifier. The sensing circuit is configured to sense pixel information of an OLED pixel circuit through a sensing line of the OLED display panel. The operational amplifier includes an amplifier circuit and at least one switch circuit. The amplifier circuit includes at least one gain circuit. An input terminal of the amplifier circuit is coupled to an output terminal of the sensing circuit. Each of the at least one switch circuit is coupled between a pair of output terminals of a corresponding one of the at least one gain circuit.
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公开(公告)号：US10326411B2
公开(公告)日：2019-06-18
申请号：US15802617
申请日：2017-11-03
发明人： Chih-Wen Lu , Chih-Hsien Chou , Po-Yu Tseng , Jhih-Siou Cheng
摘要： An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.
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公开(公告)号：US10283069B2
公开(公告)日：2019-05-07
申请号：US15954609
申请日：2018-04-17
发明人： Ju-Lin Huang , Jhih-Siou Cheng
IPC分类号： G09G3/36 , G02F1/1362
摘要： A display panel including a plurality of pixel units, a plurality of source lines, a plurality of gate lines and a plurality of common electrode lines is provided. The pixels units are arranged in array. The array includes a plurality of columns and a plurality of rows. The source lines are respectively coupled with the pixel units disposed in a same column of the columns. The gate lines are respectively coupled with the pixel units disposed in a same row of the rows. The common electrode lines and gate lines extend parallelly with each other. At least one of the source date lines, the gate lines and the common electrode lines has the line widths varied along the extension direction thereof.
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公开(公告)号：US10163416B2
公开(公告)日：2018-12-25
申请号：US14801855
申请日：2015-07-17
发明人： Chieh-An Lin , Jhih-Siou Cheng , Po-Hsiang Fang , Po-Yu Tseng , Ju-Lin Huang , Yi-Chuan Liu
IPC分类号： G09G3/36
摘要： A display apparatus and a driving method of the same are provided. The display apparatus includes a display panel, a gate driver circuit, and a source driver circuit. During a functional sub-period of a frame period, the gate driver circuit simultaneously drives a plurality of gate lines, and the source driver circuit drives a plurality of source lines, so as to perform a function on a plurality of pixels connected to the gate lines. In a scan sub-period of the frame period, the gate driver circuit drives the gate lines according to a scan sequence, and the source driver circuit correspondingly drives the source lines according to the scan sequence of the gate driver circuit in the first scan sub-period, so as to display an image.
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48.发明申请公开(公告)号：US20180337642A1
公开(公告)日：2018-11-22
申请号：US15802617
申请日：2017-11-03
发明人： Chih-Wen Lu , Chih-Hsien Chou , Po-Yu Tseng , Jhih-Siou Cheng
CPC分类号： H03F1/3205 , H03F1/086 , H03F1/301 , H03F1/3211 , H03F1/523 , H03F3/45183 , H03F3/4521 , H03F3/45219 , H03F3/45237 , H03F3/45381 , H03F3/45632 , H03F2203/45342 , H03F2203/45352 , H03F2203/45382 , H03F2203/45384 , H03K17/063 , H03K17/0822
摘要： An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.
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公开(公告)号：US09875711B2
公开(公告)日：2018-01-23
申请号：US15016295
申请日：2016-02-05
发明人： Po-Hsiang Fang , Jhih-Siou Cheng
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2310/0251 , G09G2310/0286 , G09G2310/08
摘要： A gate driver and an operation method thereof are provided. The gate driver includes clock transmission wires and driving circuits. The clock transmission wires are configured to transmit clock signals having different phases. Each of the driving circuits has a clock input terminal, a pre-charge terminal, a discharge control terminal and an output terminal. The output terminals are configured to drive gate lines of a display panel. The driving circuits are grouped into several driving circuit groups. The driving circuits belonging to a first driving circuit group among the driving circuit groups are called first driving circuits. The clock input terminals of the first driving circuits are coupled to different transmission wires among the clock transmission wires. The pre-charge terminals of the first driving circuits commonly receive a first pre-charge signal. The discharge control terminals of the first driving circuits commonly receive a first discharge control signal.
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公开(公告)号：US09842528B2
公开(公告)日：2017-12-12
申请号：US15256753
申请日：2016-09-06
发明人： Po-Yu Tseng , Jhih-Siou Cheng , Pang-Chen Hung
IPC分类号： G09G3/3275 , G09G3/20
CPC分类号： G09G3/20 , G09G2310/027 , G09G2310/0289 , G09G2330/025 , G09G2330/045
摘要： A driving device is provided. The driving device includes a first code mapping circuit, a first source driving channel, a second code mapping circuit and a second source driving channel. The first code mapping circuit converts a first input code in input data into a first intermediate code according to a first code-to-code mapping relation. The first source driving channel converts the first intermediate code into a first analog voltage according to a first code-to-voltage mapping relation. The second code mapping circuit converts a second input code in the input data into a second intennediate code according to a second code-to-code mapping relation which is different from the first code-to-code mapping relation. The second source driving channel converts the second intermediate code into a second analog voltage according to a second code-to-voltage mapping relation which is different from the first code-to-voltage mapping relation.
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