公开(公告)号：US08054892B2

公开(公告)日：2011-11-08

申请号：US12370230

申请日：2009-02-12

申请人： Pervez M. Aziz ,  Adam Healey ,  Shawn Logan

发明人： Pervez M. Aziz ,  Adam Healey ,  Shawn Logan

IPC分类号： H04B3/00 ,  H04L25/00

CPC分类号： H04L25/03885 ,  H04L1/203

摘要： Described embodiments provide a method and system for signal compensation in a SERDES communication system that includes monitoring the quality of a data signal after passing through a transmission channel. The quality of the data signal is monitored with at least one of a BER calculation algorithm and a received eye quality monitoring algorithm. Variations in channel length of the transmission channel are compensated for by i) adjusting a length of transmission line delay of the data signal from the transmission channel, ii) comparing the data signal quality with a threshold for the adjusted data signal; and iii) repeating i) and ii) until the data signal quality meets the threshold.

摘要翻译： 所描述的实施例提供了一种在SERDES通信系统中用于信号补偿的方法和系统，其包括在通过传输信道之后监视数据信号的质量。 使用BER计算算法和接收到的眼睛质量监视算法中的至少一个来监视数据信号的质量。 通过i）调整来自传输信道的数据信号的传输线延迟的长度来补偿传输信道的信道长度的变化，ii）将数据信号质量与调整数据信号的阈值进行比较; 和iii）重复i）和ii）直到数据信号质量满足阈值。

公开(公告)号：US07792234B2

公开(公告)日：2010-09-07

申请号：US11414521

申请日：2006-04-28

申请人： Pervez M. Aziz ,  Gregory W. Sheets ,  Vladimir Sindalovsky

发明人： Pervez M. Aziz ,  Gregory W. Sheets ,  Vladimir Sindalovsky

IPC分类号： H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H03L7/0807 ,  H03L7/087 ,  H03L7/093 ,  H04L7/0004 ,  H04L7/0331

摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.

摘要翻译： 提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。 还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。 通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。

公开(公告)号：US20100202498A1

公开(公告)日：2010-08-12

申请号：US12370230

申请日：2009-02-12

申请人： Pervez M. Aziz ,  Adam Healey ,  Shawn Logan

发明人： Pervez M. Aziz ,  Adam Healey ,  Shawn Logan

IPC分类号： H04B1/40

CPC分类号： H04L25/03885 ,  H04L1/203

摘要： Described embodiments provide a method and system for signal compensation in a SERDES communication system that includes monitoring the quality of a data signal after passing through a transmission channel. The quality of the data signal is monitored with at least one of a BER calculation algorithm and a received eye quality monitoring algorithm. Variations in channel length of the transmission channel are compensated for by i) adjusting a length of transmission line delay of the data signal from the transmission channel, ii) comparing the data signal quality with a threshold for the adjusted data signal; and iii) repeating i) and ii) until the data signal quality meets the threshold.

摘要翻译： 所描述的实施例提供了一种在SERDES通信系统中用于信号补偿的方法和系统，其包括在通过传输信道之后监视数据信号的质量。 使用BER计算算法和接收到的眼睛质量监视算法中的至少一个来监视数据信号的质量。 通过i）调整来自传输信道的数据信号的传输线延迟的长度来补偿传输信道的信道长度的变化，ii）将数据信号质量与调整数据信号的阈值进行比较; 和iii）重复i）和ii）直到数据信号质量满足阈值。

公开(公告)号：US07167328B2

公开(公告)日：2007-01-23

申请号：US11223090

申请日：2005-09-09

申请人： Viswanath Annampedu ,  Pervez M. Aziz

发明人： Viswanath Annampedu ,  Pervez M. Aziz

IPC分类号： G11B5/09 ,  G11B21/10 ,  G11B5/02

CPC分类号： G11B20/10009 ,  G11B2020/1484

摘要： A first set of data is detected in a signal having synchronous samples and interpolated samples, wherein the first set of data is detected asynchronously as corresponding to one of the samples. A time to transmit a data-found signal is determined based on an offset between the data-detected sample and one of the synchronous samples, and the data-found signal is transmitted at the determined time to enable the synchronous processing of the synchronous samples. In one implementation, the synchronous samples correspond to a readback signal read from a data recording channel, the first set of data corresponds to servo address mark (SAM) data in a servo sector in the readback signal, and the synchronous processing is demodulation of burst data in the servo sector.

摘要翻译： 在具有同步采样和内插采样的信号中检测第一组数据，其中第一组数据被异步地检测为对应于一个采样。 基于数据检测样本与同步样本中的一个之间的偏移来确定发送数据发现信号的时间，并且在确定的时间发送数据发现的信号，以使能同步采样的同步处理。 在一个实现中，同步采样对应于从数据记录通道读取的回读信号，第一组数据对应于回读信号中的伺服扇区中的伺服地址标记（SAM）数据，并且同步处理是脉冲串的解调 数据在伺服扇区。

公开(公告)号：US07092462B2

公开(公告)日：2006-08-15

申请号：US10342153

申请日：2003-01-14

申请人： Viswanath Annampedu ,  Pervez M. Aziz

发明人： Viswanath Annampedu ,  Pervez M. Aziz

IPC分类号： H03D1/00 ,  H04L27/06

CPC分类号： G11B5/59627

摘要： A repeatable read-out (RRO) detector employs one or more digital interpolators to interpolate asynchronous sample values that represent RRO data. The asynchronous sample values are read from a recording medium and generated by an A/D converter at a symbol rate, and the interpolators generate interpolated samples at at least one time in between the asynchronous sample value times. Each interpolated sample corresponding to some phase relative to that of the sample values generated by the A/D converter. The RRO detector receives 1) the asynchronous samples at symbol rate and 2) the interpolated samples to efficiently detect the encoded RRO data. An RRO address mark indicates when detection of encoded RRO data starts, and is employed to select those samples suitable for RRO data detection. Detection of the RRO address mark employs peak detection among filtered asynchronous and interpolated samples. The process of peak detection adjusts the current best phase for sample selection. When the RRO address mark is found, the corresponding best phase corresponds to either asynchronous sampled values or interpolated samples that are subsequently selected for RRO data detection, termed best samples. Once the best phase is selected, the RRO data detector uses that information along with RRO encoding constraints to decode the encoded RRO data from the best samples.

公开(公告)号：US06912099B2

公开(公告)日：2005-06-28

申请号：US10436526

申请日：2003-05-13

申请人： Viswanath Annampedu ,  Pervez M. Aziz

发明人： Viswanath Annampedu ,  Pervez M. Aziz

IPC分类号： G11B5/596 ,  G11B20/10 ,  G11B20/18 ,  H04L7/02 ,  H04L25/03

CPC分类号： H04L7/0054 ,  G11B5/59627 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/10296 ,  H04L25/03191

摘要： A repeatable run-out (RRO) detector employs one or more digital interpolators to interpolate asynchronous sample values representing an RRO address mark (AM) and RRO data, an asynchronous maximum-likelihood (AML) detector to detect the RRO AM, and a RRO data decoder to decode the RRO data. The AML detector employs an AML algorithm, such as a Viterbi algorithm, to detect the series of peaks of the RRO AM based on detection of the entire sequence of observed peaks. AML detection selects one of either the asynchronous or interpolated sample sequences that are closest in distance to the ideal RRO AM sample sequence. Once the RRO AM is detected, the AML detector provides a RRO AM found signal as well as the selected one of the sample sequences having the best phase for detecting and decoding the RRO data.

摘要翻译： 可重复耗尽（RRO）检测器使用一个或多个数字内插器内插表示RRO地址标记（AM）和RRO数据的异步采样值，用于检测RRO AM的异步最大似然（AML）检测器和RRO 数据解码器来解码RRO数据。 AML检测器采用AML算法，例如维特比算法，根据检测到的观察峰的整个序列来检测RRO AM的一系列峰。 AML检测选择与理想RRO AM样本序列距离最近的异步或内插样本序列之一。 一旦检测到RRO AM，AML检测器提供了一个RRO AM发现的信号，以及所选择的一个采样序列具有检测和解码RRO数据的最佳相位。

公开(公告)号：US06751774B2

公开(公告)日：2004-06-15

申请号：US10366837

申请日：2003-02-14

申请人： Pervez M. Aziz

发明人： Pervez M. Aziz

IPC分类号： H03M1303

CPC分类号： G11B20/10287 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/1426 ,  H03M5/145

摘要： A system for block encoding and block decoding of servo data with a rate (M/N) code, where M is an integer greater than 1 and N is an integer that is greater than M. Two codes are described for the encoding and decoding processes: a rate (2/6) code and a rate (2/8) code. In general, block encoding and block decoding maps between M servo data bits and N coded symbol bits. Such block encoding with a rate (M/N) code may be employed in a magnetic recording system for encoding servo data that is written to a servo data sector on a magnetic recording medium. Encoded servo data is read from the magnetic medium and block decoded. A forced maximum-likelihood, partial-response (PRML) detector is used to detect the N coded symbol bits from channel samples read from the magnetic medium. Block encoding provides greater coding gain for a detector when the characteristics of the block code are used to improve performance of the PRML detector that is used to detect the N coded symbol bits. Such PRML detector may employ a Viterbi algorithm (VA). State transition decisions over a block of N channel samples, or N clock cycles, form a path through a trellis of the VA, and the characteristics of the block code are used to force decisions for state transitions in the trellis. The PRML detector may force a decision for each state transition based on a priori knowledge of the known valid transitions defined by the rate (M/N) code symbol bits.

摘要翻译： 一种利用速率（M / N）码对伺服数据进行块编码和块解码的系统，其中M是大于1的整数，N是大于M的整数。描述了编码和解码过程的两个代码 ：代码（2/6）和代码（2/8）。 通常，块编码和块解码映射在M个伺服数据位和N个编码符号位之间。 在磁记录系统中可以采用具有速率（M / N）码的这种块编码，用于对写在磁记录介质上的伺服数据扇区的伺服数据进行编码。 编码伺服数据从磁介质读取并进行解码。 使用强制最大似然，部分响应（PRML）检测器来从磁介质读取的信道样本中检测N个编码符号位。 当块代码的特性用于提高用于检测N个编码符号位的PRML检测器的性能时，块编码为检测器提供更大的编码增益。 这种PRML检测器可以采用维特比算法（Viterbi algorithm）。 在N个通道样本块或N个时钟周期上的状态转换决策形成通过VA的网格的路径，并且使用块代码的特征来强制格架中的状态转换的决定。 PRML检测器可以基于由速率（M / N）码符号位定义的已知有效转换的先验知识来强制对每个状态转换的决定。

公开(公告)号：US20130230093A1

公开(公告)日：2013-09-05

申请号：US13540923

申请日：2012-07-03

申请人： Pervez M. Aziz ,  Hiroshi Kimura ,  Amaresh V. Malipatil ,  Hairong Gao

发明人： Pervez M. Aziz ,  Hiroshi Kimura ,  Amaresh V. Malipatil ,  Hairong Gao

IPC分类号： H04L27/01

CPC分类号： H04L25/14 ,  H04L25/03057 ,  H04L25/03885 ,  H04L2025/0349 ,  H04L2025/03579

摘要： Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.

摘要翻译： 描述的实施例通过一组固定抽头和接收器的一组浮动抽头接收信号，每个抽头对应于检测到的符号。 每个浮动抽头存储在相应的移位寄存器中，以解决接收器的过程，工作电压和温度（PVT）变化，而不校准延迟元件。 多路复用逻辑通过将选定的浮动抽头耦合到固定抽头的输出端，选择（i）相应的浮动抽头进行均衡，以及（ii）每个可能的浮动抽头位置的不同相位。 多路复用逻辑修剪和/或合并每个可能的浮动抽头位置的相位，并且基于每相的幅度选择浮动抽头。 组合器通过相应的抽头调整固定抽头和所选浮动抽头的每个输出值，将调整后的值组合成输出信号，并从输入信号中减去输出信号。

公开(公告)号：US07606301B2

公开(公告)日：2009-10-20

申请号：US11356690

申请日：2006-02-17

申请人： Pervez M. Aziz

发明人： Pervez M. Aziz

IPC分类号： H03H7/30

CPC分类号： H04L25/03057 ,  H04L7/0332

摘要： Methods and apparatus are provided for adaptively establishing the optimal sampling phase offset for a DFE operation. According to one aspect of the invention, one or more values in an amplitude domain are converted into a time domain, for example, using a phase detector, based on phase information to provide said sampling phase. The values in the amplitude domain optionally comprise one or more of detected DFE data, ŷ(n) and a sign of an error term for detected DFE data. The sampling phase can establish the phase of an independent clock or an offset to a second clock, such as a clock recovered from a received signal by a clock and data recovery (CDR) circuit.

摘要翻译： 提供了用于自适应地建立DFE操作的最佳采样相位偏移的方法和装置。 根据本发明的一个方面，幅度域中的一个或多个值被转换成时域，例如，使用相位检测器，基于相位信息来提供所述采样相位。 幅度域中的值可选地包括检测到的DFE数据，y（n）中的一个或多个以及用于检测到的DFE数据的误差项的符号。 采样相位可以建立独立时钟或偏移到第二时钟的相位，例如通过时钟和数据恢复（CDR）电路从接收信号恢复的时钟。

公开(公告)号：US07466766B2

公开(公告)日：2008-12-16

申请号：US11728862

申请日：2007-03-27

申请人： Pervez M. Aziz

发明人： Pervez M. Aziz

IPC分类号： H04L25/06

CPC分类号： H04L25/061

摘要： A read channel component of a magnetic recording system employs equalization of a signal received from the magnetic recording channel, the equalization being modified depending upon the presence or absence of DC shifts in the signal. Equalization corrects for DC shifts, if present, prior to detection and decoding of servo data, such as servo address mark (SAM) and Gray code data. In a first implementation, a DC shift detector detects the presence or absence of DC shifts and modifies equalization in a predetermined manner. In a second implementation, filtering is applied to the signal to enhance equalization in the presence of DC shift, and both filtered and unfiltered signals employed for detection of the servo data.

摘要翻译： 磁记录系统的读通道部件使用从磁记录通道接收的信号的均衡，根据信号中是否存在直流偏移来修正均衡。 在检测和解码伺服数据（如伺服地址标记（SAM））和格雷码数据之前，均衡校正直流偏移（如果存在）。 在第一实施例中，DC移位检测器检测DC偏移的存在或不存在，并以预定方式修改均衡。 在第二实施例中，对信号进行滤波以增强存在DC偏移的均衡，以及用于检测伺服数据的滤波和未滤波信号。