-
1.发明申请公开(公告)号：US20130230093A1
公开(公告)日：2013-09-05
申请号：US13540923
申请日：2012-07-03
IPC分类号： H04L27/01
CPC分类号： H04L25/14 , H04L25/03057 , H04L25/03885 , H04L2025/0349 , H04L2025/03579
摘要： Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.
摘要翻译： 描述的实施例通过一组固定抽头和接收器的一组浮动抽头接收信号，每个抽头对应于检测到的符号。 每个浮动抽头存储在相应的移位寄存器中，以解决接收器的过程，工作电压和温度（PVT）变化，而不校准延迟元件。 多路复用逻辑通过将选定的浮动抽头耦合到固定抽头的输出端，选择（i）相应的浮动抽头进行均衡，以及（ii）每个可能的浮动抽头位置的不同相位。 多路复用逻辑修剪和/或合并每个可能的浮动抽头位置的相位，并且基于每相的幅度选择浮动抽头。 组合器通过相应的抽头调整固定抽头和所选浮动抽头的每个输出值，将调整后的值组合成输出信号，并从输入信号中减去输出信号。
-
2.发明授权公开(公告)号：US08743945B2
公开(公告)日：2014-06-03
申请号：US13540923
申请日：2012-07-03
IPC分类号： H03H7/30
CPC分类号： H04L25/14 , H04L25/03057 , H04L25/03885 , H04L2025/0349 , H04L2025/03579
摘要： Described embodiments receive a signal by a set of fixed taps and a set of floating taps of a receiver, each tap corresponding to a detected symbol. Each of the floating taps is stored in a corresponding shift register to account for process, operating voltage and temperature (PVT) variations of the receiver without calibration of delay elements. Multiplexing logic selects (i) corresponding floating taps for equalization by coupling selected floating taps to the outputs of the fixed taps, and (ii) different phases of each possible floating tap position. The multiplexing logic prunes and/or amalgamates the phases of each possible floating tap position and selects floating taps based on a magnitude of each phase. A combiner adjusts each output value of the fixed taps and the selected floating taps by a corresponding tap-weight, combines the adjusted values into an output signal and subtracts the output signal from the input signal.
摘要翻译： 描述的实施例通过一组固定抽头和接收器的一组浮动抽头接收信号，每个抽头对应于检测到的符号。 每个浮动抽头存储在相应的移位寄存器中，以解决接收器的过程，工作电压和温度（PVT）变化，而不校准延迟元件。 多路复用逻辑通过将选定的浮动抽头耦合到固定抽头的输出端，选择（i）相应的浮动抽头进行均衡，以及（ii）每个可能的浮动抽头位置的不同相位。 多路复用逻辑修剪和/或合并每个可能的浮动抽头位置的相位，并且基于每相的幅度选择浮动抽头。 组合器通过相应的抽头调整固定抽头和所选浮动抽头的每个输出值，将调整后的值组合成输出信号，并从输入信号中减去输出信号。
-
公开(公告)号：US20130142245A1
公开(公告)日：2013-06-06
申请号：US13312443
申请日：2011-12-06
申请人： Vladimir Sindalovsky , Mohammed S. Mobin , Lane A. Smith , Amaresh V. Malipatil , Pervez M. Aziz
发明人： Vladimir Sindalovsky , Mohammed S. Mobin , Lane A. Smith , Amaresh V. Malipatil , Pervez M. Aziz
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L2025/03636 , H04L2025/03694
摘要： In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.
摘要翻译： 在所描述的实施例中，串行器解串器（SerDes）接收器包括模式检测器，其允许检测到不充分随机的模式周期和低活动期。 在这些时期内冻结均衡适应可能会通过将不合格的模式嵌入到适应数据中来实现。 一些实施例还允许检测长的冻结间隔，并且因此延迟冻结断言以便接收器的时钟和数据恢复（CDR）电路重新获得对串行数据的锁定。 在接收数据中嵌入冻结信息可以精确地同步接收数据并进行冻结。
-
公开(公告)号：US08548038B2
公开(公告)日：2013-10-01
申请号：US13312443
申请日：2011-12-06
申请人： Vladimir Sindalovsky , Mohammad S. Mobin , Lane A. Smith , Amaresh V. Malipatil , Pervez M. Aziz
发明人： Vladimir Sindalovsky , Mohammad S. Mobin , Lane A. Smith , Amaresh V. Malipatil , Pervez M. Aziz
IPC分类号： H03H7/40
CPC分类号： H04L25/03057 , H04L2025/03636 , H04L2025/03694
摘要： In described embodiments, a Serializer-Deserializer (SerDes) receiver includes a pattern detector that allows for detection of insufficiently randomized pattern periods and low activity periods. A freeze of equalization adaptation during these periods might occur by embedding disqualifying patterns into adaptation data. Some embodiments also allow for detection of long intervals of freeze, and so delay a freeze de-assertion in order for a clock and data recovery (CDR) circuit of the receiver to regain lock to the serial data. Embedding freeze information in the receive data allows for precise synchronization of receive data and freeze.
摘要翻译： 在所描述的实施例中，串行器解串器（SerDes）接收器包括模式检测器，其允许检测到不充分随机的模式周期和低活动期。 在这些时期内冻结均衡适应可能会通过将不合格的模式嵌入到适应数据中来实现。 一些实施例还允许检测长的冻结间隔，并且因此延迟冻结断言以便接收器的时钟和数据恢复（CDR）电路重新获得对串行数据的锁定。 在接收数据中嵌入冻结信息可以精确地同步接收数据并进行冻结。
-
公开(公告)号：US08761237B2
公开(公告)日：2014-06-24
申请号：US13288096
申请日：2011-11-03
申请人： Pervez M. Aziz , Hiroshi Kimura
发明人： Pervez M. Aziz , Hiroshi Kimura
CPC分类号： H03F3/195 , H03F3/211 , H03F3/45183 , H03F2200/294 , H03F2203/45454 , H03F2203/45466 , H03F2203/45701 , H03G5/165 , H04L25/03057
摘要： A variable gain amplifier (VGA) useful in a receiver that recovers transmitted digital signals. A first amplifier in the VGA has a first gain, an input coupled to an input of the VGA, and an output coupled to a load. A second amplifier in the VGA has a second gain, an input coupled to the input of the VGA, and an output coupled to the load. In a first mode of operation, the first gain is substantially zero and the second gain ranges between a maximum gain and a fraction of the maximum gain. In a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain and the fraction of the maximum gain, and an algebraic sum of the first gain and second gain is no greater than the maximum gain to reduce non-linear distortion at low VGA gain.
摘要翻译： 一种可变增益放大器（VGA），可用于恢复传输的数字信号的接收机。 VGA中的第一放大器具有第一增益，耦合到VGA的输入的输入和耦合到负载的输出。 VGA中的第二放大器具有第二增益，耦合到VGA的输入的输入和耦合到负载的输出。 在第一工作模式中，第一增益基本为零，第二增益范围为最大增益和最大增益的一部分。 在第二种操作模式中，第一增益基本上是最大增益，第二增益在最大增益和最大增益分数之间的范围内，第一增益和第二增益的代数和不大于 在低VGA增益下降低非线性失真。
-
公开(公告)号：US20130114665A1
公开(公告)日：2013-05-09
申请号：US13288096
申请日：2011-11-03
申请人： Pervez M. Aziz , Hiroshi Kimura
发明人： Pervez M. Aziz , Hiroshi Kimura
CPC分类号： H03F3/195 , H03F3/211 , H03F3/45183 , H03F2200/294 , H03F2203/45454 , H03F2203/45466 , H03F2203/45701 , H03G5/165 , H04L25/03057
摘要： A variable gain amplifier (VGA) useful in a receiver that recovers transmitted digital signals. A first amplifier in the VGA has a first gain, an input coupled to an input of the VGA, and an output coupled to a load. A second amplifier in the VGA has a second gain, an input coupled to the input of the VGA, and an output coupled to the load. In a first mode of operation, the first gain is substantially zero and the second gain ranges between a maximum gain and a fraction of the maximum gain. In a second mode of operation the first gain is substantially the maximum gain and the second gain ranges between the maximum gain and the fraction of the maximum gain, and an algebraic sum of the first gain and second gain is no greater than the maximum gain to reduce non-linear distortion at low VGA gain.
摘要翻译： 一种可变增益放大器（VGA），可用于恢复传输的数字信号的接收机。 VGA中的第一放大器具有第一增益，耦合到VGA的输入的输入和耦合到负载的输出。 VGA中的第二放大器具有第二增益，耦合到VGA的输入的输入和耦合到负载的输出。 在第一工作模式中，第一增益基本为零，第二增益范围为最大增益和最大增益的一部分。 在第二种操作模式中，第一增益基本上是最大增益，第二增益在最大增益和最大增益分数之间的范围内，第一增益和第二增益的代数和不大于 在低VGA增益下降低非线性失真。
-
7.发明申请公开(公告)号：US20130148712A1
公开(公告)日：2013-06-13
申请号：US13315831
申请日：2011-12-09
申请人： Amaresh Malipatil , Pervez M. Aziz , Mohammad S. Mobin , Ye Liu
发明人： Amaresh Malipatil , Pervez M. Aziz , Mohammad S. Mobin , Ye Liu
IPC分类号： H04L27/01
CPC分类号： H04L25/03057 , H04L7/033 , H04L7/0331 , H04L25/0292 , H04L25/0307 , H04L25/03159 , H04L25/03885 , H04L2025/03636 , H04L2025/037
摘要： Described embodiments adjust configurable parameters of at least one filter of a communication system. The method includes conditioning, by an analog front end (AFE) of a receiver in the communication system, an input signal applied to the receiver. Sampled values of the conditioned input signal are generated and digitized. An error detection module generates an error signal based on digitized values of the input signal and a target value. A decision feedback equalizer generates an adjustment signal based on the digitized values of the input signal and values of the error signal. A summer subtracts the adjustment signal from the conditioned input signal, generating an adjusted input signal. An adaptation module determines a conditional adaptation signal based on a comparison of sampled values of the adjusted input signal and values of the error signal. The adaptation module adjusts a transfer function of at least one filter based on the conditional adaptation signal.
摘要翻译： 描述的实施例调整通信系统的至少一个滤波器的可配置参数。 该方法包括通过通信系统中的接收机的模拟前端（AFE）调整施加到接收机的输入信号。 生成调节输入信号的采样值并进行数字化。 误差检测模块基于输入信号的数字化值和目标值产生误差信号。 判决反馈均衡器基于输入信号的数字化值和误差信号的值生成调整信号。 夏季从调节的输入信号中减去调整信号，产生经调整的输入信号。 适应模块基于经调整的输入信号的采样值和误差信号的值的比较来确定条件适配信号。 适应模块基于条件适应信号来调整至少一个滤波器的传递函数。
-
8.发明授权Method and apparatus for integral state initialization and quality of lock monitoring in a clock and data recovery system 有权用于整体状态初始化的方法和装置以及时钟和数据恢复系统中锁定监视的质量公开(公告)号：US08416907B2
公开(公告)日：2013-04-09
申请号：US12846390
申请日：2010-07-29
CPC分类号： H03L7/0807 , H03L7/087 , H03L7/093 , H04L7/0004 , H04L7/0331
摘要： Methods and apparatus are provided for improving the performance of second order CDR systems. The integral state of the CDR system is initialized to a value that is based on an expected frequency profile that may be known a priori for certain applications. One or more quality of lock (QOL) metrics are also monitored that are derived from the integral register state value. A quality of a locking between a received signal and a local clock generated by a Clock and Data Recovery (CDR) system is evaluated by monitoring a state value of an integral register in a digital loop filter of the CDR system; evaluating one or more predefined criteria based on the integral register state value; and identifying a poor lock condition if the one or more predefined criteria are not satisfied.
摘要翻译： 提供了用于提高二级CDR系统的性能的方法和装置。 CDR系统的整体状态被初始化为基于对于某些应用可以是先验已知的预期频率分布的值。 还监视从积分寄存器状态值导出的一个或多个锁定质量（QOL）度量。 通过监视CDR系统的数字环路滤波器中的积分寄存器的状态值来评估由时钟和数据恢复（CDR）系统产生的接收信号和本地时钟之间的锁定的质量; 基于积分寄存器状态值来评估一个或多个预定标准; 并且如果不满足一个或多个预定标准，则识别差的锁定条件。
-
9.发明申请公开(公告)号：US20120014460A1
公开(公告)日：2012-01-19
申请号：US13243190
申请日：2011-09-23
申请人： Pervez M. Aziz , Adam Healey , Shawn Logan
发明人： Pervez M. Aziz , Adam Healey , Shawn Logan
CPC分类号： H04L25/03885 , H04L1/203
摘要： Described embodiments provide a method and system for signal compensation in a SERDES communication system that includes monitoring the quality of a data signal after passing through a transmission channel. The quality of the data signal is monitored with at least one of a BER calculation algorithm and a received eye quality monitoring algorithm. Variations in channel length of the transmission channel are compensated for by i) adjusting a length of transmission line delay of the data signal from the transmission channel, ii) comparing the data signal quality with a threshold for the adjusted data signal; and iii) repeating i) and ii) until the data signal quality meets the threshold.
摘要翻译： 所描述的实施例提供了一种在SERDES通信系统中用于信号补偿的方法和系统，其包括在通过传输信道之后监视数据信号的质量。 使用BER计算算法和接收到的眼睛质量监视算法中的至少一个来监视数据信号的质量。 通过i）调整来自传输信道的数据信号的传输线延迟的长度来补偿传输信道的信道长度的变化，ii）将数据信号质量与调整数据信号的阈值进行比较; 和iii）重复i）和ii）直到数据信号质量满足阈值。
-
公开(公告)号：US08027409B2
公开(公告)日：2011-09-27
申请号：US11962409
申请日：2007-12-21
IPC分类号： H03K9/00
CPC分类号： H04L25/03057 , H03K5/135 , H03M9/00
摘要： In an exemplary embodiment, noise prediction-based data detection is described with respect to a SERDES (serializer/deserializer) backplane primary channel subject to inter-symbol interference (ISI) noise and added cross-talk noise from other channels. Noise prediction-based data detection combines an added error component from inter-symbol interference (ISI) noise and an added error component from cross-talk noise into an overall noise prediction error term and cancels effects of residual ISI and cross-talk for various components of the exemplary embodiment.
摘要翻译： 在示例性实施例中，关于经由符号间干扰（ISI）噪声的SERDES（串行器/解串行器）背板主信道和来自其他信道的增加的串扰噪声来描述基于噪声预测的数据检测。 基于噪声预测的数据检测将来自符号间干扰（ISI）噪声的附加误差分量和来自串扰噪声的附加误差分量组合成总体噪声预测误差项，并消除各种组件的残留ISI和串扰的影响 的示例性实施例。
-
-
-
-
-
-
-
-
-
搜索结果
54 条记录 (耗时 0.027 秒)
