公开(公告)号：US20140346581A1

公开(公告)日：2014-11-27

申请号：US14283243

申请日：2014-05-21

Applicant: Renesas Electronics Corporation

Inventor： Yasushi Ishii ,  Hiraku Chakihara

IPC: H01L27/115 ,  H01L49/02

CPC classification number: H01L23/5223 ,  H01L21/28273 ,  H01L21/76805 ,  H01L21/76895 ,  H01L27/11521 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/7885 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The performances of a semiconductor device are improved. A semiconductor device has a first electrode and a dummy electrode formed apart from each other over a semiconductor substrate, a second electrode formed between the first electrode and the dummy electrode, at the circumferential side surface of the first electrode, and at the circumferential side surface of the dummy electrode, and a capacitive insulation film formed between the first electrode and the second electrode. The first electrode, the second electrode, and the capacitive insulation film form a capacitive element. Further, the semiconductor device has a first plug penetrating through the interlayer insulation film, and electrically coupled with the first electrode, and a second plug penetrating through the interlayer insulation film, and electrically coupled with the portion of the second electrode formed at the side surface of the dummy electrode opposite to the first electrode side.

Abstract translation: 提高了半导体器件的性能。 半导体器件具有在半导体衬底上彼此分开形成的第一电极和虚拟电极，形成在第一电极和虚拟电极之间的第二电极，在第一电极的周向侧表面处，并且在周向侧表面 以及形成在第一电极和第二电极之间的电容绝缘膜。 第一电极，第二电极和电容绝缘膜形成电容元件。 此外，半导体器件具有穿过层间绝缘膜并与第一电极电耦合的第一插塞和穿过层间绝缘膜的第二插塞，并且与形成在侧表面处的第二电极的部分电连接 与第一电极侧相对的虚拟电极。

公开(公告)号：US20140239378A1

公开(公告)日：2014-08-28

申请号：US14190183

申请日：2014-02-26

Applicant: Renesas Electronics Corporation

Inventor： Koichi Toba ,  Hiraku Chakihara ,  Yoshiyuki Kawashima

IPC: H01L29/792 ,  H01L29/66

CPC classification number: H01L29/792 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/66833

Abstract: In an MONOS-type memory cell with a split gate structure, short circuit between a selection gate electrode and a memory gate electrode is prevented, and reliability of a semiconductor device is improved. In a MONOS memory having a selection gate electrode and a memory gate electrode that are adjacent to each other and that extend in a first direction, an upper surface of the selection gate electrode in a region except for a shunt portion at an end portion of the selection gate electrode in the first direction is covered with a cap insulating film. The memory gate electrode is terminated on the cap insulating film side with respect to a border between the cap insulating film and an upper surface of the shunt portion exposed from the cap insulating film.

Abstract translation: 在具有分离栅极结构的MONOS型存储单元中，防止了选择栅电极和存储栅电极之间的短路，提高了半导体器件的可靠性。 在具有彼此相邻并且沿第一方向延伸的选择栅电极和存储栅电极的MONOS存储器中，在除了在第一方向的端部处的分流部分之外的区域中的选择栅电极的上表面 第一方向的选择栅极电极被帽绝缘膜覆盖。 存储栅电极相对于帽绝缘膜与从帽绝缘膜露出的分流部的上表面之间的边界在帽绝缘膜侧终止。

公开(公告)号：US08809934B2

公开(公告)日：2014-08-19

申请号：US13958574

申请日：2013-08-04

Applicant: Renesas Electronics Corporation

Inventor： Hiraku Chakihara ,  Yasushi Ishii

IPC: H01L29/788 ,  H01L21/8238 ,  H01L29/792 ,  H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L21/28273 ,  G11C16/0466 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11573 ,  H01L29/42324 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792

Abstract: A lamination pattern having a control gate electrode, a first insulation film thereover, and a second insulation film thereover is formed over a semiconductor substrate. A memory gate electrode is formed adjacent to the lamination pattern. A gate insulation film is formed between the control gate and the semiconductor substrate. A fourth insulation film, including a lamination film of a silicon oxide film, a silicon nitride film, and another silicon oxide film, is formed between the memory gate electrode and the semiconductor substrate and between the lamination pattern and the memory gate electrode. At the sidewall on the side of the lamination pattern adjacent to the memory gate electrode, the first insulation film is retreated from the control gate electrode and the second insulation film, and the upper end corner portion of the control gate electrode is rounded.

Abstract translation: 在半导体衬底上形成具有控制栅电极，其上的第一绝缘膜和其上的第二绝缘膜的叠层图案。 与层压图案相邻地形成存储栅电极。 在控制栅极和半导体衬底之间形成栅极绝缘膜。 在存储栅电极和半导体衬底之间以及叠层图案和存储栅电极之间形成第四绝缘膜，其包括氧化硅膜的叠层膜，氮化硅膜和另一氧化硅膜。 在与存储栅电极相邻的层叠图案侧的侧壁处，第一绝缘膜从控制栅极电极和第二绝缘膜退回，并且控制栅电极的上端角部分被倒圆。

公开(公告)号：US20140077310A1

公开(公告)日：2014-03-20

申请号：US14089959

申请日：2013-11-26

Applicant: Renesas Electronics Corporation

Inventor： Yasushi Ishii ,  Hiraku Chakihara ,  Kentaro Saito

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/82 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864

Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.

Abstract translation: 在包括在相同基板上具有不同特性的多个场效应晶体管的半导体器件的制造成品率方面的改进。 通过将各向异性干法蚀刻与各向同性湿蚀刻或各向同性干法蚀刻相结合，形成具有不同侧壁长度的三种类型的侧壁。 通过减少各向异性干蚀刻步骤的数量，在布置密度高的第三n型MISFET区域和第三p型MISFET区域中，可以防止半导体衬底在n型栅极之间被部分切割 彼此相邻的n型栅电极和彼此相邻的p型栅极之间，以及彼此相邻的p型栅电极。

公开(公告)号：US08617974B2

公开(公告)日：2013-12-31

申请号：US13662509

申请日：2012-10-28

Applicant: Renesas Electronics Corporation

Inventor： Yasushi Ishii ,  Hiraku Chakihara ,  Kentaro Saito

IPC: H01L21/3205

CPC classification number: H01L27/088 ,  H01L21/28008 ,  H01L21/82 ,  H01L21/823425 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864

Abstract: An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.