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公开(公告)号：US06639534B2
公开(公告)日：2003-10-28
申请号：US10076087
申请日：2002-02-14
IPC分类号： H03M166
CPC分类号： H03M1/0678 , H03M1/0863 , H03M1/66
摘要： A digital-to-analog conversion circuit includes first and second DACs. Switch circuitry couples a selected output of only one of the DACs to an output node at any given time. In one embodiment, a second output of the first DAC is coupled to the first output of the second DAC at a common node. The first output of the first DAC is coupled to a first switch node and a second output of the second DAC is coupled to a second switch node. A first switch couples the common node to the first switch node in response to a first switch signal. A second switch couples the common node to the second switch node in response to a second switch signal. The switch signals ensure that the common node is coupled through the first and second switches to only one of the first and second switch nodes at any given time.
摘要翻译： 数模转换电路包括第一和第二DAC。 在任何给定的时间，开关电路将选择的仅一个DAC的输出耦合到输出节点。 在一个实施例中，第一DAC的第二输出在公共节点处耦合到第二DAC的第一输出。 第一DAC的第一输出耦合到第一开关节点，并且第二DAC的第二输出耦合到第二开关节点。 第一开关响应于第一开关信号将公共节点耦合到第一开关节点。 响应于第二开关信号，第二开关将公共节点耦合到第二开关节点。 开关信号确保在任何给定时间，公共节点通过第一和第二开关耦合到仅第一和第二开关节点中的一个。
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42.发明授权
公开(公告)号：US5986281A
公开(公告)日：1999-11-16
申请号：US956409
申请日：1997-10-23
CPC分类号： G01R31/2858
摘要： A circuit and method for detecting mobile ion contamination in a semiconductor device. The circuit uses two transistor structures on the same silicon chip as the circuit being tested to detect the presence (or absence) of mobile ions. The test includes imposing conditions on the silicon chip that may cause any mobile ions present therein to move within the structure. By measuring electrical parameters, such as a band gap voltage, across the transistors before and after the imposition of such conditions, a reliable indication of the presence or absence of mobile ions can be obtained.
摘要翻译： 一种用于检测半导体器件中的移动离子污染的电路和方法。 该电路在与被测电路相同的硅芯片上使用两个晶体管结构来检测移动离子的存在（或不存在）。 测试包括在硅芯片上施加可能导致其中存在的任何移动离子在结构内移动的条件。 通过在施加这种条件之前和之后测量跨越晶体管的电参数，例如带隙电压，可以获得是否存在移动离子的可靠指示。
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43.发明授权公开(公告)号：US07599673B2
公开(公告)日：2009-10-06
申请号：US11240814
申请日：2005-09-30
申请人： Adrian Maxim , Ramin Khoini-Poorfard , James Kao
发明人： Adrian Maxim , Ramin Khoini-Poorfard , James Kao
IPC分类号： H04B1/18
CPC分类号： H04N7/20 , H03D3/006 , H03D3/007 , H03J1/0066 , H03K3/0322 , H03L7/18 , H04H40/90 , H04N5/4401 , H04N5/4446 , H04N5/50 , H04N21/4263
摘要： A technique includes receiving a signal spectrum that includes a plurality of channels within a first frequency range. The technique includes receiving a selection signal that identifies at least one desired channel to be tuned. The technique includes providing an oscillator that has a second frequency range that is substantially the same as the first frequency range and controlling the oscillators to generate one of a plurality of coarse-tune analog mixing signals. The signals substantially span across the second frequency range and each depends upon the location of the desired channel within the signal spectrum. The technique includes mixing the signal spectrum with the selected coarse-tune analog mixing signal to generate a coarsely tuned signal spectrum. The technique includes digitally processing the coarsely-tuned signal spectrum to fine tune the desired channel and to produce digital baseband signals for the desired channel.
摘要翻译： 一种技术包括在第一频率范围内接收包括多个信道的信号频谱。 该技术包括接收标识要调谐的至少一个期望信道的选择信号。 该技术包括提供具有与第一频率范围基本相同的第二频率范围的振荡器，并且控制振荡器以产生多个粗调模拟混合信号之一。 信号基本跨越第二频率范围，并且每个信号取决于信号频谱内期望信道的位置。 该技术包括将信号频谱与所选择的粗调模拟混合信号混合以产生粗调谐信号频谱。 该技术包括对粗调谐信号频谱进行数字处理以微调所需信道并产生所需信道的数字基带信号。
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44.发明授权Multi-tuner integrated circuit architecture utilizing frequency isolated local oscillators and associated method 有权使用频率隔离的本地振荡器的多调谐器集成电路架构及相关方法公开(公告)号：US07447491B2
公开(公告)日：2008-11-04
申请号：US10456215
申请日：2003-06-06
IPC分类号： H04B1/10
摘要： Integrated multiple tuner architectures and associated methods are disclosed that utilize frequency isolated local oscillators (LO). These architectures utilize dividers and multipliers within the signal paths for the local oscillator mixing signals to reduce interference among the multiple local oscillators operating on a single integrated circuit. A multiple tuner direct-down-conversion (DDC) receiver and a multiple tuner intermediate frequency (IF) receiver are provided as example embodiments. And an example integrated multi-tuner satellite receiver is also described.
摘要翻译： 公开了利用频率隔离的本地振荡器（LO）的集成多调谐器架构和相关联的方法。 这些架构在本地振荡器混合信号的信号路径内使用分频器和乘法器，以减少在单个集成电路上工作的多个本地振荡器之间的干扰。 作为示例实施例，提供了多调谐器直接下变频（DDC）接收机和多调谐器中频（IF）接收机。 并且还描述了一个集成的多调谐器卫星接收机的示例。
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公开(公告)号：US20050243949A1
公开(公告)日：2005-11-03
申请号：US10836775
申请日：2004-04-30
CPC分类号： H04L27/364
摘要： Timing correction is effected for mismatch between channels in an I/Q demodulator. The respective demodulated I-channel and Q-channel are correlated and integrated so generate a timing control signal that is applied to a variable delay element. The variable delay element inserts a variable time delay in an ADC clock signal that is applied to either the I-channel ADC or the Q-channel ADC.
摘要翻译： 对I / Q解调器通道之间的失配进行定时校正。 相应的解调的I信道和Q信道被相关和积分，从而产生应用于可变延迟元件的定时控制信号。 可变延迟元件在应用于I通道ADC或Q通道ADC的ADC时钟信号中插入可变时间延迟。
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46.发明申请Integrated receiver decoder for receiving digitally modulated signals from a satellite 审中-公开用于从卫星接收数字调制信号的集成接收机解码器公开(公告)号：US20050066367A1
公开(公告)日：2005-03-24
申请号：US10664554
申请日：2003-09-19
IPC分类号： H04N7/20
CPC分类号： H04N7/20
摘要： An integrated receiver decoder for receiving digitally modulated signals from a satellite is disclosed. The receiver includes a tuner, a demodulator, a low-noise block (LNB) controller, a voltage controller and a voltage selector implemented within a single monolithic integrated circuit device. The tuner amplifies and filters satellite signals received from a directional receiver antenna. The demodulator, which is coupled to the tuner, demodulates and decodes the received satellite signals. The LNB controller generates and detects a modulated tone to facilitate communications between the receiver and an LNB feed attached to the directional receiver antenna. The voltage selector directs the voltage controller to provide a control signal for controlling an external voltage regulator to generate a variable voltage to the LNB feed attached to the directional receiver antenna.
摘要翻译： 公开了一种用于从卫星接收数字调制信号的集成接收机解码器。 接收机包括调谐器，解调器，低噪声块（LNB）控制器，电压控制器和在单个单片集成电路器件内实现的电压选择器。 调谐器放大并滤波从定向接收机天线接收的卫星信号。 耦合到调谐器的解调器解调并解码所接收的卫星信号。 LNB控制器产生和检测调制音，以便于接收机与附接到定向接收机天线的LNB馈送之间的通信。 电压选择器引导电压控制器提供用于控制外部电压调节器的控制信号，以向连接到定向接收机天线的LNB馈电产生可变电压。
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公开(公告)号：US06865235B2
公开(公告)日：2005-03-08
申请号：US09800192
申请日：2001-03-06
CPC分类号： H04L27/0012
摘要： A multi-protocol modulator capable of supporting two or more different modes of operation, each mode of operation corresponding to a different type of modulation, comprises an m-level phase shift keying (m-PSK) modulator which receives a serial input data stream and maps data contained therein into a constellation including m equidistant phases in accordance with a predetermined mapping scheme. The m-PSK modulator is shared by at least two different modulation protocols by allowing the mapping scheme to be selectively changed depending upon the modulation protocol used. The multi-protocol modulator further includes a phase rotator operatively coupled to the output of the m-PSK modulator. The phase rotator selectively rotates the phase of the m-PSK signal by a predetermined phase rotation value. The phase rotator is shared by the two or more modulation protocols by allowing the phase rotation value to be selectively modified depending upon the modulation protocol used. A phase rotated signal is then passed through a pulse shaping filter having a linearized Gaussian response.
摘要翻译： 一种能够支持两种或多种不同操作模式的多协议调制器，每种模式对应于不同类型的调制，包括接收串行输入数据流的m级相移键控（m-PSK）调制器， 将包含在其中的数据根据预定的映射方案映射到包括m个等距离相位的星座。 m-PSK调制器由至少两种不同的调制协议共享，允许根据所使用的调制协议选择性地改变映射方案。 多协议调制器还包括可操作地耦合到m-PSK调制器的输出的相位旋转器。 相位旋转器选择性地使m-PSK信号的相位旋转预定的相位旋转值。 相位旋转器由两个或更多个调制协议共享，允许相位旋转值根据所使用的调制协议被选择性地修改。 相位旋转信号然后通过具有线性化高斯响应的脉冲整形滤波器。
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48.发明申请Apparatus and method for carrier feedthrough cancellation in RF upconverters 审中-公开RF上变频器载波馈通消除的装置和方法公开(公告)号：US20050020205A1
公开(公告)日：2005-01-27
申请号：US10626062
申请日：2003-07-23
摘要： An RF upconverter (400, 500) includes an upconverter core (100), an electrical measurement circuit, and a summing device (406). The upconverter core (100) has an input terminal for receiving a first signal having predetermined spectral content at an input frequency and an output terminal for providing an output signal having substantially the predetermined spectral content at a higher frequency using a local oscillator signal having a carrier frequency. The electrical measurement circuit has an input terminal coupled to the output terminal of the upconverter core (100), and an output terminal for providing a first offset correction signal representative of a power of the output signal at the carrier frequency. The summing device (406) has a positive input terminal for receiving a first input signal, a negative input terminal coupled to the output terminal of the electrical measurement circuit, and an output terminal coupled to the input terminal of the upconverter core (100) for providing the first signal.
摘要翻译： RF上变频器（400,500）包括上变频器内核（100），电测量电路和求和装置（406）。 上变频器内核（100）具有用于在输入频率处接收具有预定频谱含量的第一信号的输入端子和用于使用具有载波的本地振荡器信号以更高频率提供具有基本上预定频谱含量的输出信号的输出端 频率。 电测量电路具有耦合到上变频器核（100）的输出端的输入端和用于提供代表载波频率的输出信号的功率的第一偏移校正信号的输出端。 求和装置（406）具有用于接收第一输入信号的正输入端子，耦合到电测量电路的输出端子的负输入端子和耦合到上变频器芯线（100）的输入端子的输出端子，用于 提供第一个信号。
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公开(公告)号：US6151613A
公开(公告)日：2000-11-21
申请号：US172376
申请日：1998-10-14
CPC分类号： H03H17/0614
摘要： A digital filter receives signals from each stage of a MASH delta-sigma modulator and filters noise components from the signals prior to combination as a single sequence of values decimation. Each stage of the MASH delta-sigma modulator provides an output sequence of one-bit, binary values, which are then filtered to remove high-order, out of band quantization noise. After filtering, the output sequences are then combined through a cascade-combiner, which may be similar to the pre-processing stage of a MASH delta-sigma modulator architecture. The digital filter processes signals of each stage separately. Consequently, the digital filter does not perform multiplication of two, multi-bit values. Multiplication of two values, the first of which is a one-bit, binary value, may be implemented with a multiplexer selecting either the second value or a zero value based on the first one-bit, binary value (i.e., logic 1 or 0, respectively). Duplicate FIR filters, or a single FIR filter with bit-interleaving by a multiplexer, master-slave delay chain and demultiplexer controlled by system clock transitions, may be used to process the sequences on a single bit basis, replacing multi-bit multipliers of the digital filter with multiplexers. Alternatively, the FIR filter may be implemented with a multiplexer, master-slave delay chain, ROM look-up table and demultiplexer if bit interleaving is employed.
摘要翻译： 数字滤波器从MASHΔ-Σ调制器的每个级接收信号，并且将来自组合之前的信号的噪声分量作为单个值抽取序列进行滤波。 MASH delta-sigma调制器的每个级提供一位二进制值的输出序列，然后将其过滤以去除高阶带外量化噪声。 在滤波之后，然后通过级联组合器组合输出序列，其可以类似于MASH delta-sigma调制器架构的预处理阶段。 数字滤波器分别处理每个级的信号。 因此，数字滤波器不执行两个多位值的乘法。 可以通过多路复用器来实现两个值的乘法，其中第一个值是一位二进制值，该多路复用器基于第一个一位二进制值（即逻辑1或0）选择第二值或零值 ， 分别）。 复用FIR滤波器或具有由多路复用器进行位交织的单个FIR滤波器，由系统时钟转换控制的主从延迟链和解复用器可用于以单个位为基础来处理序列，取代多位乘法器 带多路复用器的数字滤波器 或者，如果使用比特交织，则可以用多路复用器，主从延迟链，ROM查找表和解复用器来实现FIR滤波器。
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50.发明授权Resistor string with equal resistance resistors and converter incorporating the same 失效具有等电阻电阻的电阻串和包含相同电阻的转换器
公开(公告)号：US5977897A
公开(公告)日：1999-11-02
申请号：US775211
申请日：1996-12-31
CPC分类号： H01C3/12 , H01L27/0802
摘要： An integrated circuit includes a string of substantially similarly-shaped resistive cells, each cell having a first resistive portion and a second resistive portion, the string having an overall orientation and at least one cell, preferably substantially all cells, and more preferably all cells have their respective centerlines oriented at non-orthogonal angles, preferably about 45 degrees, relative to the overall orientation. The cells are contiguous such that a resistor is formed by the first resistive portion of one cell and the second resistive portion of an adjacent cell. The cells preferably have a substantially hexagonal shape and are arranged into substrings. If the string includes a folding point, substrings immediately adjacent to the folding point should include an odd number, preferably three, of cells, and substrings not adjacent to the folding point should comprise an even number, preferably two, of cells. Preferably, the hexagonally shaped cells include two longer sides and four shorter sides, each cell having a tap substantially centrally positioned along one of its longer sides, a resistor being formed between the taps of any two adjacent cells. The taps are preferably arranged to form a grid such that each tap is aligned with at least one other tap substantially parallel to the overall orientation and each tap is aligned with at least one other tap substantially perpendicular to the overall orientation. A converter, such as a digital-to-analog converter (DAC) or an analog-to-digital converter (ADC) includes such a resistor string.
摘要翻译： 集成电路包括一串基本相似形状的电阻单元，每个单元具有第一电阻部分和第二电阻部分，该串具有整体取向和至少一个电池，优选基本上全部电池，更优选所有电池均具有 它们各自的中心线相对于整个取向定向在非正交角度，优选地为大约45度。 电池是连续的，使得电阻器由一个电池的第一电阻部分和相邻电池的第二电阻部分形成。 细胞优选具有基本上六边形的形状并且被排列成子串。 如果字符串包括折叠点，则紧邻折叠点的子串应包括奇数，优选三个单元，并且不邻近折叠点的子串应包括偶数，优选两个单元。 优选地，六边形形状的单元包括两个较长的边和四个较短的边，每个单元具有沿着其较长边中的一个大致中心定位的抽头，在两个相邻单元的抽头之间形成电阻器。 抽头优选地布置成形成网格，使得每个抽头与基本上平行于整个取向的至少一个其他抽头对准，并且每个抽头与基本上垂直于整个取向的至少一个其他抽头对准。 A转换器，例如数模转换器（DAC）或模数转换器（ADC）包括这样的电阻串。
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