公开(公告)号：US20150340480A1

公开(公告)日：2015-11-26

申请号：US14715648

申请日：2015-05-19

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/36 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7813

Abstract: A switching loss is prevented from being deteriorated by suppressing increase in a gate capacitance due to a cell shrink of an IE type trench gate IGBT. A cell formation region is configured of a linear active cell region, a linear hole collector cell region, and a linear inactive cell region between them. Then, upper surfaces of the third and fourth linear trench gate electrodes which are formed so as to sandwich both sides of the linear hole collector cell region and electrically connected to an emitter electrode are positioned to be lower than upper surfaces of the first and second linear trench gate electrodes which are formed so as to sandwich both sides of the linear active cell region and electrically connected to a gate electrode.

Abstract translation: 通过抑制由于IE型沟槽栅极IGBT的电池收缩引起的栅极电容的增加，防止了开关损耗的劣化。 细胞形成区域由线状有源单元区域，线状空穴集电极区域和它们之间的线性非活性单元区域构成。 然后，形成为夹着线状空穴集电室区域的两侧并电连接到发射极的第三和第四线性沟槽栅电极的上表面被定位成低于第一和第二线性电极的上表面 沟槽栅极电极，其形成为夹着线性有源电池区域的两侧并电连接到栅电极。