公开(公告)号：US20180261693A1

公开(公告)日：2018-09-13

申请号：US15976991

申请日：2018-05-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/40 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.

公开(公告)号：US20180083130A1

公开(公告)日：2018-03-22

申请号：US15824523

申请日：2017-11-28

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7396 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4238 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device includes trench gate electrodes, an emitter coupling section that couples them with each other, an interlayer insulating film arranged in a hybrid sub-cell region and an inactive cell region, and a contact trench penetrating it. Also, the contact trench is divided in a crossing region of extending directions of the hybrid sub-cell region and the emitter coupling section. Further, an n+-type emitter region is disposed so as to be apart from an end of the divided contact trench. With such configuration of not forming the contact trench in the crossing region, the working failure of the contact trench can be reduced. Also, because the n+-type emitter region is disposed so as to be apart from the end of the contact trench, the breakdown resistance of the semiconductor device can be improved.

公开(公告)号：US20170358530A1

公开(公告)日：2017-12-14

申请号：US15665540

申请日：2017-08-01

Applicant: Renesas Electronics Corporation

Inventor： Yukio TAKAHASHI ,  Hitoshi MATSUURA

IPC: H01L23/525 ,  H01L29/739 ,  H01L29/06 ,  H01L27/02 ,  H01L29/40 ,  H01L23/522 ,  H01L29/66 ,  H01L21/66

CPC classification number: H01L23/5258 ,  H01L22/22 ,  H01L23/5228 ,  H01L27/0255 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.

公开(公告)号：US20170154984A1

公开(公告)日：2017-06-01

申请号：US15355469

申请日：2016-11-18

Applicant: Renesas Electronics Corporation

Inventor： Satoshi EGUCHI ,  Hitoshi MATSUURA ,  Yuya ABIKO

IPC: H01L29/739 ,  H01L21/324 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/32

CPC classification number: H01L29/7396 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/32 ,  H01L29/404 ,  H01L29/66333 ,  H01L29/6634

Abstract: Reduction of power consumption of a semiconductor device is aimed. The semiconductor device includes a cell region where a vertical power MOSFET is formed and an intermediate region surrounding the cell region. In each of the cell region and the intermediate region, a plurality of p-type column regions and a plurality of n-type column regions are alternately formed. The n-type column region arranged in the cell region has a defect region formed therein, whereas the n-type column region arranged in the intermediate region does not have the defect region. A defect density in the n-type column region arranged in the cell region is larger than that in the n-type column region arranged in the intermediate region.

公开(公告)号：US20140145260A1

公开(公告)日：2014-05-29

申请号：US14170430

申请日：2014-01-31

Applicant: Renesas Electronics Corporation

Inventor： Hitoshi MATSUURA ,  Yoshito NAKAZAWA ,  Tsuyoshi KACHI ,  Yuji YATSUDA

IPC: H01L27/06 ,  H01L29/872 ,  H01L29/78

CPC classification number: H01L27/0629 ,  H01L21/26586 ,  H01L21/76897 ,  H01L29/0615 ,  H01L29/086 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/8725

Abstract: A gate trench 13 is formed in a semiconductor substrate 10. The gate trench 13 is provided with a gate electrode 16 formed over a gate insulating film 14. A portion of the gate electrode 16 protrudes from the semiconductor substrate 10, and a sidewall 24 is formed over a side wall portion of the protruding portion. A body trench 25 is formed in alignment with an adjacent gate electrode 16. A cobalt silicide film 28 is formed over a surface of the gate electrode 16 and over a surface of the body trench 25. A plug 34 is formed using an SAC technique.

Abstract translation: 栅极沟槽13形成在半导体衬底10中。栅极沟槽13设置有形成在栅极绝缘膜14上的栅电极16.栅电极16的一部分从半导体衬底10突出，侧壁24为 形成在突出部分的侧壁部分上。 形成与相邻的栅电极16对准的主体沟槽25.在栅电极16的表面上并在主体沟槽25的表面之上形成硅化钴膜28.使用SAC技术形成插塞34。

公开(公告)号：US20130175574A1

公开(公告)日：2013-07-11

申请号：US13733211

申请日：2013-01-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/66 ,  H01L29/739

CPC classification number: H01L29/7397 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/7395 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of further enhancing the performance of a narrow active cell IE type trench gate IGBT having the width of active cells narrower than that of inactive cells, it is effective to shrink the cells so that the IE effects are enhanced. However, when the cells are shrunk simply, the switching speed is reduced due to increased gate capacitance. A cell formation area of the IE type trench gate IGBT is basically composed of first linear unit cell areas having linear active cell areas, second linear unit cell areas having linear hole collector areas and linear inactive cell areas disposed therebetween.

公开(公告)号：US20240178277A1

公开(公告)日：2024-05-30

申请号：US18523734

申请日：2023-11-29

Applicant: Renesas Electronics Corporation

Inventor： Katsumi EIKYU ,  Ryota KURODA ,  Hitoshi MATSUURA ,  Sho NAKANISHI

IPC: H01L29/08 ,  H01L21/265 ,  H01L21/266 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/0804 ,  H01L21/26513 ,  H01L21/266 ,  H01L29/0696 ,  H01L29/41708 ,  H01L29/66348 ,  H01L29/7397

Abstract: A semiconductor substrate includes a plurality of emitter formation regions separated from each other in a Y direction between a pair of trenches, and a separation region located between the emitter formation regions. A p-type base region is formed in the semiconductor substrate of each of the emitter formation regions and the separation region. An n-type impurity region is formed in the base region of each emitter formation region. The impurity region is also formed in the base region at a position in contact with the pair of trenches in the separation region.

公开(公告)号：US20230127197A1

公开(公告)日：2023-04-27

申请号：US17892660

申请日：2022-08-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L27/06 ,  H01L29/739 ,  H01L21/265 ,  H01L29/66

Abstract: A semiconductor device includes a semiconductor substrate, a gate insulating film, a gate, and a first polysilicon film. The semiconductor substrate has a first main surface and a second main surface that is an opposite surface of the first main surface. The semiconductor substrate has a first portion and a second portion. The semiconductor substrate is a collector region arranged on the second main surface located in the first portion, a cathode region arranged on the second main surface located in the second portion, a drift region arranged on the collector region and the cathode region, an emitter region arranged on the first main surface located in the first portion, a base region arranged between the emitter region and the collector region, and an anode region arranged on the first main surface located in the second portion.

公开(公告)号：US20180053838A1

公开(公告)日：2018-02-22

申请号：US15785027

申请日：2017-10-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hitoshi MATSUURA

IPC: H01L29/739 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L23/535 ,  H01L29/40 ,  H01L21/768 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7397 ,  H01L21/76895 ,  H01L23/535 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1004 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41725 ,  H01L29/4236 ,  H01L29/66348

Abstract: The surface of an interlayer insulating film formed over an emitter coupling portion and the surface of an emitter electrode formed over the interlayer insulating film are caused to have a gentle shape, in particular, at the end of the emitter coupling portion, by forming the emitter coupling portion over a main surface of a semiconductor substrate and integrally with trench gate electrodes in order to form a spacer over the sidewall of the emitter coupling portion. Thereby, stress is dispersed, not concentrated in an acute angle portion of the emitter coupling portion when an emitter wire is coupled to the emitter electrode (emitter pad), and hence occurrence of a crack can be suppressed. Further, by forming the spacer, the concavities and convexities to be formed in the surface of the emitter electrode can be reduced, whereby the adhesiveness between the emitter electrode and the emitter wire can be improved.

公开(公告)号：US20180040612A1

公开(公告)日：2018-02-08

申请号：US15600729

申请日：2017-05-20

Applicant: Renesas Electronics Corporation

Inventor： Yukio TAKAHASHI ,  Hitoshi MATSUURA

IPC: H01L27/082 ,  H01L29/423 ,  H01L27/088

CPC classification number: H01L27/0825 ,  H01L27/088 ,  H01L29/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/7397

Abstract: To improve current detection performance of a sense IGBT particularly in a low current region in a semiconductor device equipped with a main IGBT and the sense IGBT used for current detection of the main IGBT. At a peripheral portion located at an outermost periphery of an active region surrounded by a dummy region within a sense IGBT cell, an n+-type semiconductor region is formed over an upper surface of a well of a floating state adjacent to a trench gate electrode embedded into a trench at an upper surface of a semiconductor substrate and applied with a gate voltage.