-
公开(公告)号：US20110261871A1
公开(公告)日：2011-10-27
申请号：US13175594
申请日：2011-07-01
IPC分类号： H04B17/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δfmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.
摘要翻译： 全数字频率合成器架构围绕数字控制振荡器（DCO）构建，该振荡器响应于数字调谐字（OTW）进行调谐。 在示例性实施例中：（1）数字控制振荡器的增益特性（KDCO）可以通过在振荡频率中的已知变化（＆Dgr; fmax）之前和之后观察数字控制字来确定; 和（2）调谐字的一部分（TUNE_TF）可以被抖动（1202），并且所得到的抖动部分（dkTF）然后可以被施加到数字控制振荡器内的可切换装置的控制输入。
-
公开(公告)号：US08000428B2
公开(公告)日：2011-08-16
申请号：US10302029
申请日：2002-11-22
IPC分类号： H04L7/00
CPC分类号： H03L7/085 , H03L7/0991 , H03L2207/50
摘要： An all-digital frequency synthesizer architecture is built around a digitally controlled oscillator (DCO) that is tuned in response to a digital tuning word (OTW). In exemplary embodiments: (1) a gain characteristic (KDCO) of the digitally controlled oscillator can be determined by observing a digital control word before and after a known change (Δfmax) in the oscillating frequency; and (2) a portion (TUNE_TF) of the tuning word can be dithered (1202), and the resultant dithered portion (dkTF) can then be applied to a control input of switchable devices within the digitally controlled oscillator.
摘要翻译： 全数字频率合成器架构围绕数字控制振荡器（DCO）构建，该振荡器响应于数字调谐字（OTW）进行调谐。 在示例性实施例中：（1）数字控制振荡器的增益特性（KDCO）可以通过在振荡频率中的已知变化（＆Dgr; fmax）之前和之后观察数字控制字来确定; 和（2）调谐字的一部分（TUNE_TF）可以被抖动（1202），并且所得到的抖动部分（dkTF）然后可以被施加到数字控制振荡器内的可切换装置的控制输入。
-
43.发明授权Method of defining semiconductor fabrication process utilizing transistor inverter delay period 有权利用晶体管反相器延迟周期定义半导体制造工艺的方法公开(公告)号：US07813462B2
公开(公告)日：2010-10-12
申请号：US11550878
申请日：2006-10-19
IPC分类号： H03D3/24
CPC分类号： H04L27/361 , H03L7/091 , H03L7/0991 , H03L7/1806
摘要： A novel method and apparatus for defining process variation in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The method and apparatus provide direct measurement of fabrication process variation in circuits without requiring any additional test equipment by utilizing a time to digital converter (TDC) circuit already present in the chip. The TDC circuit relies on the time delay in an inverter chain to sample a high speed CKV clock using a slow FREF clock. Calculation of inverse time provides a direct correlation for fabrication process variation in each die.
摘要翻译： 一种用于定义数字RF处理器（DRP）中的处理变化的新颖方法和装置。 本发明非常适用于结合了大量数字逻辑电路的高度集成的片上系统（SoC）无线电解决方案。 该方法和装置提供对电路中制造工艺变化的直接测量，而不需要使用已经存在于芯片中的时间 - 数字转换器（TDC）电路的任何额外的测试设备。 TDC电路依赖于逆变器链中的时间延迟，使用缓慢的FREF时钟采样高速CKV时钟。 逆时间的计算提供了每个模具中制造工艺变化的直接相关性。
-
公开(公告)号：US07667511B2
公开(公告)日：2010-02-23
申请号：US11195060
申请日：2005-08-02
IPC分类号： H03K3/017
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
摘要翻译： 由PAM调制器提供有效的PAM发射调制，PAM调制器包括提供时钟信号CKV（408）的振荡器（404）。 时钟信号408和时钟信号的延迟版本（CKV_DLY）420被提供给逻辑门（414）。 逻辑门（414）的输出用作射频功率放大器（416）的功率放大器输入信号（PA_IN）。 根据CKV时钟信号（408）和CKV_DLY延迟时钟信号（420）的相对时间延迟，可以控制逻辑门（414）占空比的定时和占空比。 占空比或脉冲宽度变化影响功率放大器的导通时间（416）; 从而建立RF输出振幅。
-
公开(公告)号：US06959049B2
公开(公告)日：2005-10-25
申请号：US09828338
申请日：2001-04-06
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
CPC分类号： H03D7/1441 , H03D7/125 , H03D7/1466 , H03D7/1475 , H04B1/28
摘要： A multi-tap, digital-pulse-driven mixer advantageously avoids local oscillator (11) leakage by shifting the local oscillator frequency (FLO) out of the received frequency band. Low noise figures are advantageously realized by the use of digital pulses (51, 52) as mixer drive signals (16).
摘要翻译： 多抽头数字脉冲驱动混频器有利地通过将本地振荡器频率（F LO LO）从接收频带中移位来避免本地振荡器（11）的泄漏。 通过使用数字脉冲（51,52）作为混频器驱动信号（16），有利地实现了低噪声系数。
-
公开(公告)号：US06429693B1
公开(公告)日：2002-08-06
申请号：US09608317
申请日：2000-06-30
申请人： Robert B. Staszewski , Dirk Leipold
发明人： Robert B. Staszewski , Dirk Leipold
IPC分类号： H03D324
CPC分类号： H03L7/085 , H03L7/087 , H03L7/091 , H03L2207/50
摘要： A digital fractional phase detector is provided to realize a frequency synthesizer architecture that naturally combines transmitter modulation capability with a wideband all-digital PLL modulation scheme to maximize a digitally-intensive implementation by operating in a synchronous phase domain. Synchronous logic is provided across a digitally controlled VCO and is synchronous to the VCO output clock by implementing a timing adjustment in association with a reference calculation to allow a frequency control word to contain both channel information and transmit modulation information. The digital fractional phase detector is capable of accommodating a quantization scheme to measure fractional delay differences between the significant edge of the VCO output clock and a reference clock by using a time-to-digital converter to express the time difference as a digital word for use by the frequency synthesizer.
摘要翻译： 提供数字分数相位检测器以实现频率合成器架构，其自然地将发射机调制能力与宽带全数字PLL调制方案相结合，以通过在同步相域中操作来最大化数字密集型实现。 通过实施与参考计算相关联的定时调整，跨数字控制VCO提供同步逻辑，并且与VCO输出时钟同步，以允许频率控制字包含信道信息和发送调制信息。 数字分数相位检测器能够容纳量化方案，以通过使用时间 - 数字转换器来测量VCO输出时钟的显着边缘与参考时钟之间的分数延迟差，以将时差表示为要使用的数字字 由频率合成器。
-
公开(公告)号：US08055231B2
公开(公告)日：2011-11-08
申请号：US12949461
申请日：2010-11-18
申请人： Khurram Muhammad , Meng-Chang Lee , Dirk Leipold
发明人： Khurram Muhammad , Meng-Chang Lee , Dirk Leipold
CPC分类号： H04B1/28 , H03M1/183 , H04B1/0007
摘要： Methods and apparatus to perform radio frequency (RF) analog-to-digital conversion are described. According to one example, a receiver includes an amplifier to amplify received analog RF signals and a mixer-free circuit for converting the received analog RF signals to digital signals.
摘要翻译： 描述了执行射频（RF）模数转换的方法和装置。 根据一个示例，接收机包括用于放大接收到的模拟RF信号的放大器和用于将所接收的模拟RF信号转换为数字信号的无混频器电路。
-
48.发明申请RF TRANSMISSION LEAKAGE MITIGATOR, METHOD OF MITIGATING AN RF TRANSMISSION LEAKAGE AND CDMA TRANCEIVER EMPLOYING THE SAME 有权RF传输泄漏减轻器，减少RF传输泄漏的方法和使用其的CDMA检测器公开(公告)号：US20100167655A1
公开(公告)日：2010-07-01
申请号：US12721930
申请日：2010-03-11
申请人： Khurram Muhammad , Dirk Leipold
发明人： Khurram Muhammad , Dirk Leipold
IPC分类号： H04B1/00
摘要： The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.
摘要翻译： 本发明提供了一种与全双工无线收发器一起使用的RF传输泄漏缓解器。 在一个实施例中，RF传输泄漏减轻器包括反相发生器，其被配置为将干扰收发器RF传输的RF发射反转信号提供给收发器的接收部分，从而产生残余泄漏信号。 此外，RF传输泄漏缓解器还包括耦合到反向发生器并被配置为基于将剩余泄漏信号减小到指定电平来调整干扰收发器RF传输的RF发射反转信号的残余处理器。
-
49.发明授权Digital, down-converted RF residual leakage signal mitigating RF residual leakage 有权数字，降频转换的RF残留泄漏信号可减轻RF残留泄漏公开(公告)号：US07706755B2
公开(公告)日：2010-04-27
申请号：US11270121
申请日：2005-11-09
申请人： Khurram Muhammad , Dirk Leipold
发明人： Khurram Muhammad , Dirk Leipold
IPC分类号： H04B1/40
摘要： The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.
摘要翻译： 本发明提供了一种与全双工无线收发器一起使用的RF传输泄漏缓解器。 在一个实施例中，RF传输泄漏减轻器包括反相发生器，其被配置为将干扰收发器RF传输的RF发射反转信号提供给收发器的接收部分，从而产生残余泄漏信号。 此外，RF传输泄漏缓解器还包括耦合到反向发生器并被配置为基于将剩余泄漏信号减小到指定电平来调整干扰收发器RF传输的RF发射反转信号的残余处理器。
-
50.发明授权Offset balancer, method of balancing an offset and a wireless receiver employing the balancer and the method 有权偏移平衡器，平衡偏移的方法和采用平衡器的无线接收器及其方法公开(公告)号：US07532874B2
公开(公告)日：2009-05-12
申请号：US11270122
申请日：2005-11-09
申请人： Khurram Muhammad , Dirk Leipold
发明人： Khurram Muhammad , Dirk Leipold
CPC分类号： H03D3/008
摘要： The present invention provides an offset balancer for use with a differential mixer employing a wireless reception and an offset quantifier configured to indicate an existing DC offset of the mixer corresponding to an existing second-order intercept point applicable to the wireless reception. In one embodiment, the offset balancer includes an offset adjuster coupled to the offset quantifier and configured to provide an offset adjustment to the existing DC offset based on increasing the existing second-order intercept point.
摘要翻译： 本发明提供一种与使用无线接收的差分混频器一起使用的偏移平衡器和配置为指示对应于可应用于无线接收的现有二阶截取点的混频器的现有DC偏移的偏移量化器。 在一个实施例中，偏移平衡器包括偏移调整器，该偏移调整器耦合到偏移量化器并且被配置为基于增加现有的二阶截取点来提供对现有DC偏移的偏移调整。
-
-
-
-
-
-
-
-
-
搜索结果
110 条记录 (耗时 0.029 秒)
