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公开(公告)号：US20090179302A1
公开(公告)日：2009-07-16
申请号：US12355056
申请日：2009-01-16
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A programmable device (eFuse), includes: a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having a first end (12a), a second end (12b), a fuse link (11) between the ends, and an upper surface S. The semiconductor material includes a dopant having a concentration of at least 10*17/cc. The first end (12a) is wider than the second end (12b), and a metallic material is disposed on the upper surface. The metallic material is physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and through the metallic material.
摘要翻译： 一种可编程器件（eFuse），包括：衬底（10）; 绝缘体（13）; 在绝缘体上的细长半导体材料（12），所述细长半导体材料具有第一端（12a），第二端（12b），端部之间的熔断体（11）和上表面S.半导体材料包括 浓度至少为10 * 17 / cc的掺杂剂。 第一端（12a）比第二端（12b）宽，并且金属材料设置在上表面上。 响应于可流过半导体材料和通过金属材料的电流I，金属材料可沿着上表面物理迁移。
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公开(公告)号：US07550323B2
公开(公告)日：2009-06-23
申请号：US11835800
申请日：2007-08-08
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.
摘要翻译： 在包含阴极半导体部分，熔丝半导体部分和阳极半导体部分的图案化的半导体材料层上沉积金属层。 可以对金属层进行图案化，使得熔融半导体部分的中间部分具有薄金属层，其在退火时产生比在熔融半导体部分上的周围金属半导体合金部分更薄的金属半导体合金部分。 或者，在整个整体中具有均匀厚度的金属半导体合金的中间部分可以被光刻图案化和蚀刻，以在熔丝中间形成薄金属半导体合金部分，同时在端部形成厚金属半导体合金部分 的fuselink。 所产生的本发明的电熔丝具有界面，在该界面上，较薄的金属半导体合金与所述富熔体中较厚的金属半导体合金相接触以增强电流的发散。
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43.发明申请FUSE STRUCTURE INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL LAYER AND GAP 有权保险丝结构，包括单晶半导体材料层和GAP公开(公告)号：US20090096059A1
公开(公告)日：2009-04-16
申请号：US11870007
申请日：2007-10-10
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part of the monocrystalline semiconductor material layer is separated from the substrate by a gap. Use of the monocrystalline semiconductor material layer, as well as the gap, provides for enhanced uniformity and reproducibility when programming the fuse.
摘要翻译： 熔丝结构，制造熔丝结构的方法和用于对熔丝结构内的熔丝进行编程的方法各自使用用作熔丝的熔丝材料层，并且依次位于单晶半导体材料层上而位于衬底上。 至少部分单晶半导体材料层通过间隙与衬底分离。 单晶半导体材料层的使用以及间隙，在编程保险丝时提供了增强的均匀性和再现性。
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44.发明授权Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit 失效用于表征用于个性化集成电路的电子保险丝的方法和装置公开(公告)号：US07504875B2
公开(公告)日：2009-03-17
申请号：US11923932
申请日：2007-10-25
IPC分类号： H01H37/76
CPC分类号： G01R31/31853 , G01R31/30 , G01R31/3004
摘要： An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.
摘要翻译： 提供一种具有至少一个能够被熔断以便提供熔丝电流 - 电压特性测量的熔断器的集成电路器件。 集成电路装置还提供与熔丝相关联的至少一个脉冲发生电路，并且能够产生脉冲以通过一个或多个DC输入信号来熔断熔丝。
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公开(公告)号：US20090042341A1
公开(公告)日：2009-02-12
申请号：US11835800
申请日：2007-08-08
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.
摘要翻译： 在包含阴极半导体部分，熔丝半导体部分和阳极半导体部分的图案化的半导体材料层上沉积金属层。 可以对金属层进行图案化，使得熔融半导体部分的中间部分具有薄金属层，其在退火时产生比在熔融半导体部分上的周围金属半导体合金部分更薄的金属半导体合金部分。 或者，在整个整体中具有均匀厚度的金属半导体合金的中间部分可以被光刻图案化和蚀刻，以在熔丝中间形成薄金属半导体合金部分，同时在端部形成厚金属半导体合金部分 的fuselink。 所产生的本发明的电熔丝具有界面，在该界面上，较薄的金属半导体合金与所述富熔体中较厚的金属半导体合金相接触以增强电流的发散。
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公开(公告)号：US20080232150A1
公开(公告)日：2008-09-25
申请号：US11689559
申请日：2007-03-22
IPC分类号： G11C17/00
摘要： A method and structure implementing a reprogrammable read only memory (ROM) include a pair of fuse elements having different lengths and selectively arranged to define an initial bit state. A group of a plurality of the pairs of fuse elements defines a predetermined data pattern of ones and zeros, providing initial states stored in the reprogrammable ROM. The reprogrammable ROM is reprogrammed when needed by selectively blowing a selected fuse or selected fuses to change the data pattern stored in the ROM.
摘要翻译： 实现可再编程只读存储器（ROM）的方法和结构包括具有不同长度的一对熔丝元件，并且选择性地布置以定义初始位状态。 一组多对熔丝元件定义了一个和零的预定数据模式，提供存储在可再编程ROM中的初始状态。 当需要时，通过选择性地吹送所选择的保险丝或选定的保险丝来改变存储在ROM中的数据模式，重编程ROM被重新编程。
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公开(公告)号：US20080169529A1
公开(公告)日：2008-07-17
申请号：US11622616
申请日：2007-01-12
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。
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公开(公告)号：US07388273B2
公开(公告)日：2008-06-17
申请号：US11152750
申请日：2005-06-14
申请人： Geoffrey W. Burr , Chandrasekharan Kothandaraman , Chung Hon Lam , Xiao Hu Liu , Stephen M. Rossnagel , Christy S. Tyberg , Robert L. Wisnieff
发明人： Geoffrey W. Burr , Chandrasekharan Kothandaraman , Chung Hon Lam , Xiao Hu Liu , Stephen M. Rossnagel , Christy S. Tyberg , Robert L. Wisnieff
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L23/5252 , H01L45/06 , H01L45/1206 , H01L45/1226 , H01L45/1286 , H01L45/1293 , H01L45/144 , H01L45/148 , H01L45/1683 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.
摘要翻译： 集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。 电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。 可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。 集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。
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公开(公告)号：US20080079113A1
公开(公告)日：2008-04-03
申请号：US11538170
申请日：2006-10-03
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.
摘要翻译： 熔丝结构包括插入在基板和熔丝材料层之间的空腔。 空腔不形成在熔丝材料层的侧壁处，或者在与衬底相对的熔丝材料层的表面处。 当熔丝材料层包括裂纹末端和较窄的中间区域时，可以在使用自对准蚀刻方法的同时在衬底和熔丝材料层之间形成空隙。 空隙由支撑熔丝材料层的一对牺牲层基座分开。 通过使用封装介电层将空隙封装以形成空腔。 或者，当形成插入在基板和熔丝材料层之间的空隙时，可以使用块掩模。
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50.发明申请公开(公告)号：US20080048638A1
公开(公告)日：2008-02-28
申请号：US11923932
申请日：2007-10-25
CPC分类号： G01R31/31853 , G01R31/30 , G01R31/3004
摘要： An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.
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