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公开(公告)号：US20090040006A1
公开(公告)日：2009-02-12
申请号：US11835846
申请日：2007-08-08
IPC分类号： H01H85/143 , B23P19/00
CPC分类号： G11C17/16 , Y10T29/49117
摘要： A layer of semiconductor material is patterned to form a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. A first metal layer is deposited on the patterned semiconductor material layer. A dielectric material layer is deposited and lithographically patterned to cover a middle portion of the fuselink, followed by a deposition of a second metal layer. A thin metal semiconductor alloy is formed in the middle of the fuselink and thick metal semiconductor alloy alloys are formed abutting the thin metal semiconductor alloy alloy. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink. The divergence of electrical current is enhanced at the interfaces due to a sudden change of a cross-sectional area available for current conduction.
摘要翻译： 图案化半导体材料层以形成阴极半导体部分，熔丝半导体部分和阳极半导体部分。 在图案化的半导体材料层上沉积第一金属层。 介电材料层被沉积并且被光刻图案化以覆盖该熔丝的中间部分，随后沉积第二金属层。 在熔体中间形成有薄金属半导体合金，并且与金属半导体合金合金形成邻接的厚金属半导体合金合金。 所产生的本发明的电熔丝具有界面，在该界面处，较薄的金属半导体合金与所述熔丝中的较厚的金属半导体合金相邻。 由于可用于电流传导的横截面积的突然变化，在接口处的电流的发散度增强。
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公开(公告)号：US07960809B2
公开(公告)日：2011-06-14
申请号：US12354996
申请日：2009-01-16
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.
摘要翻译： 熔丝包括熔丝链接区域，第一区域和第二区域。 熔丝链路区域将第一区域电连接到第二区域。 SiGe层仅设置在熔丝连接区域和第一区域中。
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公开(公告)号：US20100181643A1
公开(公告)日：2010-07-22
申请号：US12354996
申请日：2009-01-16
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse includes a fuse link region, a first region and a second region. The fuse link region electrically connects the first region to the second region. A SiGe layer is disposed only in the fuse link region and the first region.
摘要翻译： 熔丝包括熔丝链接区域，第一区域和第二区域。 熔丝链路区域将第一区域电连接到第二区域。 SiGe层仅设置在熔丝连接区域和第一区域中。
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公开(公告)号：US07550323B2
公开(公告)日：2009-06-23
申请号：US11835800
申请日：2007-08-08
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.
摘要翻译： 在包含阴极半导体部分，熔丝半导体部分和阳极半导体部分的图案化的半导体材料层上沉积金属层。 可以对金属层进行图案化，使得熔融半导体部分的中间部分具有薄金属层，其在退火时产生比在熔融半导体部分上的周围金属半导体合金部分更薄的金属半导体合金部分。 或者，在整个整体中具有均匀厚度的金属半导体合金的中间部分可以被光刻图案化和蚀刻，以在熔丝中间形成薄金属半导体合金部分，同时在端部形成厚金属半导体合金部分 的fuselink。 所产生的本发明的电熔丝具有界面，在该界面上，较薄的金属半导体合金与所述富熔体中较厚的金属半导体合金相接触以增强电流的发散。
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公开(公告)号：US20090042341A1
公开(公告)日：2009-02-12
申请号：US11835800
申请日：2007-08-08
IPC分类号： H01L21/82
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A metal layer is deposited on the patterned semiconductor material layer containing a cathode semiconductor portion, a fuselink semiconductor portion, and an anode semiconductor portion. The metal layer may be patterned so that a middle portion of the fuselink semiconductor portion has a thin metal layer, which upon annealing produces a thinner metal semiconductor alloy portion than surrounding metal semiconductor alloy portion on the fuselink semiconductor portion. Alternatively, a middle portion of the metal semiconductor alloy having a uniform thickness throughout the fuselink may be lithographically patterned and etched to form a thin metal semiconductor alloy portion in the middle of the fuselink, while thick metal semiconductor alloy portions are formed on the end portions of the fuselink. The resulting inventive electrical fuse has interfaces at which a thinner metal semiconductor alloy abuts a thicker metal semiconductor alloy in the fuselink to enhance the divergence of electrical current.
摘要翻译： 在包含阴极半导体部分，熔丝半导体部分和阳极半导体部分的图案化的半导体材料层上沉积金属层。 可以对金属层进行图案化，使得熔融半导体部分的中间部分具有薄金属层，其在退火时产生比在熔融半导体部分上的周围金属半导体合金部分更薄的金属半导体合金部分。 或者，在整个整体中具有均匀厚度的金属半导体合金的中间部分可以被光刻图案化和蚀刻，以在熔丝中间形成薄金属半导体合金部分，同时在端部形成厚金属半导体合金部分 的fuselink。 所产生的本发明的电熔丝具有界面，在该界面上，较薄的金属半导体合金与所述富熔体中较厚的金属半导体合金相接触以增强电流的发散。
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公开(公告)号：US08163640B2
公开(公告)日：2012-04-24
申请号：US11874385
申请日：2007-10-18
IPC分类号： H01L27/06 , H01L21/3205
CPC分类号： H01L27/0617 , H01L23/5256 , H01L29/4238 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is formed on a metal gate layer for a metal gate electrode, and then lithographically patterned to form a dielectric material portion, followed by formation of a polycrystalline semiconductor layer thereupon. A semiconductor device employing a metal gate electrode is formed in a region of the semiconductor substrate containing a vertically abutting stack of the metal gate layer and the polycrystalline semiconductor layer. A material stack in the shape of an electrical fuse is formed in another region of the semiconductor substrate containing a vertical stack of the metal gate layer, the dielectric material portion, and the polycrystalline semiconductor layer. After metallization of the polycrystalline semiconductor layer, an electrical fuse containing a polycrystalline semiconductor portion and a metal semiconductor alloy portion is formed over the dielectric material portion that separates the electrical fuse from the metal gate layer.
摘要翻译： 在用于金属栅电极的金属栅极层上形成电介质材料层，然后通过光刻图案形成电介质材料部分，随后在其上形成多晶半导体层。 在包含金属栅极层和多晶半导体层的垂直邻接堆叠的半导体基板的区域中形成采用金属栅电极的半导体器件。 形成有电熔丝形状的材料堆叠形成在半导体衬底的另一区域中，该区域包含金属栅极层，电介质材料部分和多晶半导体层的垂直叠层。 在多晶半导体层的金属化之后，在将电熔丝与金属栅极层分离开的电介质材料部分上形成包含多晶半导体部分和金属半导体合金部分的电熔丝。
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7.发明申请FUSE STRUCTURE INCLUDING MONOCRYSTALLINE SEMICONDUCTOR MATERIAL LAYER AND GAP 有权保险丝结构，包括单晶半导体材料层和GAP公开(公告)号：US20090096059A1
公开(公告)日：2009-04-16
申请号：US11870007
申请日：2007-10-10
CPC分类号： H01L23/5256 , H01L28/20 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure, a method for fabricating the fuse structure and a method for programming a fuse within the fuse structure each use a fuse material layer that is used as a fuse, and located upon a monocrystalline semiconductor material layer in turn located over a substrate. At least part of the monocrystalline semiconductor material layer is separated from the substrate by a gap. Use of the monocrystalline semiconductor material layer, as well as the gap, provides for enhanced uniformity and reproducibility when programming the fuse.
摘要翻译： 熔丝结构，制造熔丝结构的方法和用于对熔丝结构内的熔丝进行编程的方法各自使用用作熔丝的熔丝材料层，并且依次位于单晶半导体材料层上而位于衬底上。 至少部分单晶半导体材料层通过间隙与衬底分离。 单晶半导体材料层的使用以及间隙，在编程保险丝时提供了增强的均匀性和再现性。
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公开(公告)号：US20080079113A1
公开(公告)日：2008-04-03
申请号：US11538170
申请日：2006-10-03
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse structure comprises a cavity interposed between a substrate and a fuse material layer. The cavity is not formed at a sidewall of the fuse material layer, or at a surface of the fuse material layer opposite the substrate. A void may be formed interposed between the substrate and the fuse material layer while using a self-aligned etching method, when the fuse material layer comprises lobed ends and a narrower middle region. The void is separated by a pair of sacrificial layer pedestals that support the fuse material layer. The void is encapsulated to form the cavity by using an encapsulating dielectric layer. Alternatively, a block mask may be used when forming the void interposed between the substrate and the fuse material layer.
摘要翻译： 熔丝结构包括插入在基板和熔丝材料层之间的空腔。 空腔不形成在熔丝材料层的侧壁处，或者在与衬底相对的熔丝材料层的表面处。 当熔丝材料层包括裂纹末端和较窄的中间区域时，可以在使用自对准蚀刻方法的同时在衬底和熔丝材料层之间形成空隙。 空隙由支撑熔丝材料层的一对牺牲层基座分开。 通过使用封装介电层将空隙封装以形成空腔。 或者，当形成插入在基板和熔丝材料层之间的空隙时，可以使用块掩模。
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9.发明授权Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor 有权金属栅极集成结构和方法，包括金属保险丝，反熔丝和/或电阻公开(公告)号：US08159040B2
公开(公告)日：2012-04-17
申请号：US12119526
申请日：2008-05-13
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
IPC分类号： H01L29/00
CPC分类号： H01L27/0629 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.
摘要翻译： 半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成 部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。 场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。 熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料 栅电极。
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公开(公告)号：US07714326B2
公开(公告)日：2010-05-11
申请号：US11683075
申请日：2007-03-07
CPC分类号： H01L27/112 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： The present invention provides structures for antifuses that utilize electromigration for programming. By providing a portion of antifuse link with high resistance without conducting material and then by inducing electromigration of the conducting material into the antifuse link, the resistance of the antifuse structure is changed. By providing a terminal on the antifuse link, the change in the electrical properties of the antifuse link is detected and sensed. Also disclosed are an integrated antifuse with a built-in sensing device and a two dimensional array of integrated antifuses that can share programming transistors and sensing circuitry.
摘要翻译： 本发明提供了利用电迁移进行编程的反熔丝的结构。 通过在没有导电材料的情况下提供具有高电阻的一部分反熔丝连接，然后通过将导电材料电迁移到反熔丝连接中，反熔丝结构的电阻改变。 通过在反熔丝链路上设置端子，检测和感测反熔丝连接的电特性的变化。 还公开了具有内置感测装置的集成反熔丝和可共享编程晶体管和感测电路的集成反熔丝的二维阵列。
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