-
1.发明授权Method and mesh reference structures for implementing Z-axis cross-talk reduction through copper sputtering onto mesh reference planes 有权用于通过铜溅射实现Z轴串扰减少的网格参考平面的方法和网格参考结构公开(公告)号：US08053352B2
公开(公告)日：2011-11-08
申请号：US11250043
申请日：2005-10-13
IPC分类号： H01L21/4763
CPC分类号： H05K1/0224 , H05K1/0253 , H05K3/16 , H05K2201/09681 , H05K2201/09736
摘要： A method and mesh reference applications are provided for implementing Z-axis cross-talk reduction. A mesh reference plane including a grid of mesh traces is formed with the mesh traces having selected thickness and width dimensions effective for reference current-flow distribution. An electrically conductive coating is deposited to fill the mesh electrical holes in the mesh reference plane to reduce cross-talk, substantially without affecting mechanical flexibility.
摘要翻译： 提供了一种实现Z轴串扰降低的方法和网格参考应用。 包括网格轨迹的网格的网格参考平面形成为具有选定的厚度和宽度尺寸的网格轨迹对于参考电流分布有效。 沉积导电涂层以填充网格参考平面中的网格电孔，以减少串扰，基本上不影响机械灵活性。
-
2.发明授权Integrated circuits comprising resistors having different sheet resistances and methods of fabricating the same 有权包括具有不同薄片电阻的电阻器的集成电路及其制造方法公开(公告)号：US07785979B2
公开(公告)日：2010-08-31
申请号：US12173407
申请日：2008-07-15
IPC分类号： H01L21/324 , H01L21/8238
CPC分类号： H01L27/0629 , H01L28/20
摘要： The fabrication of integrated circuits comprising resistors having the same structure but different sheet resistances is disclosed herein. In one embodiment, a method of fabricating an integrated circuit comprises: concurrently forming a first resistor laterally spaced from a second resistor above or within a semiconductor substrate, the first and second resistors comprising a doped semiconductive material; depositing a dopant receiving material across the first and second resistors and the semiconductor substrate; removing the dopant receiving material from upon the first resistor while retaining the dopant receiving material upon the second resistor; and annealing the first and second resistors to cause a first sheet resistance of the first resistor to be different from a second sheet resistance of the second resistor.
摘要翻译： 本文公开了包括具有相同结构但具有不同薄层电阻的电阻器的集成电路的制造。 在一个实施例中，一种制造集成电路的方法包括：与半导体衬底之上或之内的第二电阻器横向隔开的第一电阻器同时形成，所述第一和第二电阻器包括掺杂的半导体材料; 在第一和第二电阻器和半导体衬底上沉积掺杂剂接收材料; 在所述第一电阻器上移除所述掺杂剂接收材料，同时将所述掺杂剂接收材料保持在所述第二电阻器上; 以及使所述第一和第二电阻器退火以使所述第一电阻器的第一薄层电阻与所述第二电阻器的第二薄层电阻不同。
-
公开(公告)号：US07566629B2
公开(公告)日：2009-07-28
申请号：US11155029
申请日：2005-06-16
IPC分类号： H01L21/76
CPC分类号： H01L21/76243
摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.
摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。
-
4.发明申请STRUCTURES FOR IMPLEMENTING EMI SHIELDING FOR RIGID CARDS AND FLEXIBLE CIRCUITS 审中-公开用于实施刚性卡和灵活电路的EMI屏蔽的结构公开(公告)号：US20080236883A1
公开(公告)日：2008-10-02
申请号：US12137287
申请日：2008-06-11
IPC分类号： H05K9/00
CPC分类号： H05K1/0218 , H05K1/0224 , H05K1/0253 , H05K3/061 , H05K3/3452 , H05K2201/09354 , H05K2201/09681 , H05K2201/09736 , H05K2203/0542 , H05K2203/0571
摘要： A method and structures with an EMI shielding electrically conductive coating are provided for implementing EMI shielding for rigid cards and flexible circuits. An EMI shielding electrically conductive coating is deposited on an outer layer, for example, using a vacuum sputtering deposition, chemical vapor deposition (CVD) or physical vapor deposition (PVD) process. A solder mask is applied. Mechanically cleaning removes the sputtered copper coating in areas of the outer layer that are not protected by the solder mask.
摘要翻译： 提供了具有EMI屏蔽导电涂层的方法和结构，用于实现刚性卡和柔性电路的EMI屏蔽。 EMI屏蔽导电涂层沉积在外层上，例如使用真空溅射沉积，化学气相沉积（CVD）或物理气相沉积（PVD）工艺。 使用焊接掩模。 机械清洁将外部层的不被焊接掩模保护的区域中的溅射铜涂层除去。
-
5.发明授权Method and apparatus for implementing automatic-calibration of TDR probing system 失效实现TDR探测系统自动校准的方法和装置公开(公告)号：US07299144B2
公开(公告)日：2007-11-20
申请号：US11304141
申请日：2005-12-15
申请人： Roger Allen Booth, Jr. , Matthew Stephen Doyle , Lynn Robert Landin , Thomas W. Liang , Ankur Kanu Patel
发明人： Roger Allen Booth, Jr. , Matthew Stephen Doyle , Lynn Robert Landin , Thomas W. Liang , Ankur Kanu Patel
IPC分类号： G01D18/00
CPC分类号： G01R35/00
摘要： A method and apparatus are provided for implementing automatic-calibration of a Time Domain Reflectometer (TDR) probing apparatus. A calibration procedure is performed automatically each time a TDR probe is moved from a device under test (DUT). A current calibration TDR waveform is obtained and compared with a reference calibration TDR waveform, checking for deviations between the current and reference measurements. If a deviation is detected, then the user is notified and calibration is failed.
摘要翻译： 提供了一种用于实现时域反射计（TDR）探测装置的自动校准的方法和装置。 每次TDR探针从被测设备（DUT）移动时，都会自动执行校准程序。 获得当前的校准TDR波形并与参考校准TDR波形进行比较，检查电流和参考测量之间的偏差。 如果检测到偏差，则通知用户并校准失败。
-
公开(公告)号：US20130099354A1
公开(公告)日：2013-04-25
申请号：US13279877
申请日：2011-10-24
CPC分类号： H01L29/945 , H01L29/66181
摘要： An improved semiconductor capacitor and method of fabrication is disclosed. Embodiments utilize a deep trench which is then processed by performing a pre-amorphous implant on the trench interior to transform the interior surface of the trench to amorphous silicon which eliminates the depletion region that can degrade capacitor performance.
摘要翻译： 公开了一种改进的半导体电容器和制造方法。 实施例利用深沟槽，然后通过在沟槽内部执行预非晶体植入来将沟槽的内表面转变为非晶硅来处理，以消除可能降低电容器性能的耗尽区。
-
公开(公告)号：US07659599B2
公开(公告)日：2010-02-09
申请号：US12049258
申请日：2008-03-14
IPC分类号： H01L29/00
CPC分类号： H01L21/76243
摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.
摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。
-
8.发明申请METHOD AND APPARATUS FOR IMPLEMENTING REDUCED COUPLING EFFECTS ON SINGLE ENDED CLOCKS 审中-公开对单个时钟实现减少耦合效应的方法和装置公开(公告)号：US20090189635A1
公开(公告)日：2009-07-30
申请号：US12020727
申请日：2008-01-28
申请人： Roger Allen Booth, JR. , John Richard Dangler , Matthew Stephen Doyle , Jesse Hefner , Thomas W. Liang , Ankur Kanu Patel , Paul W. Rudrud
发明人： Roger Allen Booth, JR. , John Richard Dangler , Matthew Stephen Doyle , Jesse Hefner , Thomas W. Liang , Ankur Kanu Patel , Paul W. Rudrud
IPC分类号： H03K19/003
摘要： A method and apparatus implement reduced noise coupling effects on single ended clocks, and a design structure on which the subject circuit resides is provided. A clock receiver includes a clock voltage reference that is generated from received clock peaks and valleys of a received input clock signal. The received clock peaks (VT) and the received clock valleys (VB) are continuously sampled. The clock voltage reference is set, for example, equal to an average of VT and VB; or ((VT+VB)/2).
摘要翻译： 一种方法和装置实现了对单端时钟的降低的噪声耦合效应，并且提供了主题电路所在的设计结构。 时钟接收器包括从接收到的输入时钟信号的接收时钟峰值和谷值产生的时钟参考电压。 接收的时钟峰值（VT）和接收时钟谷（VB）被连续采样。 时钟电压基准设置为例如等于VT和VB的平均值; 或（（VT + VB）/ 2）。
-
公开(公告)号：US07517764B2
公开(公告)日：2009-04-14
申请号：US11427486
申请日：2006-06-29
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。
-
公开(公告)号：US20080233699A1
公开(公告)日：2008-09-25
申请号：US12133440
申请日：2008-06-05
IPC分类号： H01L21/336
CPC分类号： H01L29/7851 , H01L29/66795
摘要： A finFET structure and a method of fabricating the finFET structure. The method includes: forming a silicon fin on a top surface of a silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode over a channel region of the fin, the gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of the channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the substrate.
摘要翻译： finFET结构和finFET结构的制造方法。 该方法包括：在硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 在鳍片的沟道区域上形成栅电极，栅电极与翅片的相对侧壁上的栅介电层直接物理接触; 在所述通道区域的第一侧上在所述翅片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和衬底之间的体接触。
-
-
-
-
-
-
-
-
-
搜索结果
34 条记录 (耗时 0.015 秒)