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公开(公告)号：US20080232152A1
公开(公告)日：2008-09-25
申请号：US11872802
申请日：2007-10-16
IPC分类号： G11C17/00
摘要： A method and structure for implementing a reprogrammable read only memory (ROM), and a design structure on which the subject circuit resides are provided. A pair of fuse elements having different lengths are selectively arranged to define an initial bit state. A group of a plurality of the pairs of fuse elements defines a predetermined data pattern of ones and zeros, providing initial states stored in the reprogrammable ROM. The reprogrammable ROM is reprogrammed when needed by selectively blowing a selected fuse or selected fuses to change the data pattern stored in the ROM.
摘要翻译： 一种用于实现可再编程只读存储器（ROM）的方法和结构，以及设置有该对象电路所在的设计结构。 选择性地布置具有不同长度的一对熔丝元件以限定初始位状态。 一组多对熔丝元件定义了一个和零的预定数据模式，提供存储在可再编程ROM中的初始状态。 当需要时，通过选择性地吹送所选择的保险丝或选定的保险丝来改变存储在ROM中的数据模式，重编程ROM被重新编程。
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公开(公告)号：US20080232150A1
公开(公告)日：2008-09-25
申请号：US11689559
申请日：2007-03-22
IPC分类号： G11C17/00
摘要： A method and structure implementing a reprogrammable read only memory (ROM) include a pair of fuse elements having different lengths and selectively arranged to define an initial bit state. A group of a plurality of the pairs of fuse elements defines a predetermined data pattern of ones and zeros, providing initial states stored in the reprogrammable ROM. The reprogrammable ROM is reprogrammed when needed by selectively blowing a selected fuse or selected fuses to change the data pattern stored in the ROM.
摘要翻译： 实现可再编程只读存储器（ROM）的方法和结构包括具有不同长度的一对熔丝元件，并且选择性地布置以定义初始位状态。 一组多对熔丝元件定义了一个和零的预定数据模式，提供存储在可再编程ROM中的初始状态。 当需要时，通过选择性地吹送所选择的保险丝或选定的保险丝来改变存储在ROM中的数据模式，重编程ROM被重新编程。
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公开(公告)号：US20100193854A1
公开(公告)日：2010-08-05
申请号：US12692923
申请日：2010-01-25
IPC分类号： H01L29/76 , H01L21/335
CPC分类号： H01L29/7923 , H01L29/66833
摘要： Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation).
摘要翻译： 热载体非易失性存储器件和用于制造热载体非易失性存储器件的方法中的每一种都取决于包括金属氧化物半导体场效应晶体管结构的半导体结构和相关方法。 半导体结构和相关方法包括以下中的至少一个：（1）包括介电常数大于7的介电材料的间隔物（用于增强热载体导电的电荷捕获和保留）; 和（2）包括半导体材料的漏极区，该半导体材料具有比半导体材料的带隙窄的带隙，其包括沟道区（用于增强的冲击电离和带电载流子的生成）。
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公开(公告)号：US08384145B2
公开(公告)日：2013-02-26
申请号：US12692923
申请日：2010-01-25
IPC分类号： H01L29/76
CPC分类号： H01L29/7923 , H01L29/66833
摘要： Each of a hot-carrier non-volatile memory device and a method for fabricating the hot carrier non-volatile memory device is predicated upon a semiconductor structure and related method that includes a metal oxide semiconductor field effect transistor structure. The semiconductor structure and related method include at least one of: (1) a spacer that comprises a dielectric material having a dielectric constant greater than 7 (for enhanced hot carrier derived charge capture and retention); and (2) a drain region that comprises a semiconductor material that has a narrower bandgap than a bandgap of a semiconductor material from which is comprised a channel region (for enhanced impact ionization and charged carrier generation).
摘要翻译： 热载体非易失性存储器件和用于制造热载体非易失性存储器件的方法中的每一种都取决于包括金属氧化物半导体场效应晶体管结构的半导体结构和相关方法。 半导体结构和相关方法包括以下中的至少一个：（1）包括介电常数大于7的介电材料的间隔物（用于增强热载体导电的电荷捕获和保留）; 和（2）包括半导体材料的漏极区，该半导体材料具有比半导体材料的带隙窄的带隙，其包括沟道区（用于增强的冲击电离和带电载流子的生成）。
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公开(公告)号：US08975910B2
公开(公告)日：2015-03-10
申请号：US13457692
申请日：2012-04-27
IPC分类号： G01R31/26 , H01L21/28 , H01L21/768 , H01L21/66 , G01R31/28
CPC分类号： H01L22/14 , G01R31/2853 , H01L21/76898 , H01L2924/00 , H01L2924/0002
摘要： A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.
摘要翻译： TSV结构，制造TSV结构的方法和TSV结构测试方法。 该结构包括：从半导体衬底的顶表面延伸到半导体衬底的底表面的沟槽，沟槽围绕半导体衬底的芯区; 在沟槽的所有侧壁上的电介质衬垫; 以及电导体填充沟槽中的所有剩余空间，电介质衬垫将电导体与半导体衬底和芯区域电隔离。
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公开(公告)号：US08950008B2
公开(公告)日：2015-02-03
申请号：US13561185
申请日：2012-07-30
CPC分类号： G06F21/73 , G06F7/588 , G06F21/00 , G06F21/30 , G06F2221/2129 , H02H3/24 , H04L9/3278
摘要： Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.
摘要翻译： 公开了用于不可发现的物理芯片识别的方法和电路。 本发明的实施例提供了包括两个晶体管的本征位元件。 两个晶体管形成一对，其中一个晶体管具有很大的阈值电压变化，另一个晶体管的阈值电压变化很小。 通过制造具有比该对中的另一个晶体管更小的宽度和长度的晶体管来实现广泛的变化。 宽变化率晶体管的阈值电压的变化意味着在内部位元素复制的情况下，一些“复制的”宽变化性晶体管将具有明显不同的阈值电压，导致一些固有位元素 复制芯片的读取方式与原始芯片的复制方式不同。
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公开(公告)号：US08629009B2
公开(公告)日：2014-01-14
申请号：US13433423
申请日：2012-03-29
IPC分类号： H01L21/336
CPC分类号： H01L29/78 , H01L21/28282 , H01L21/823462 , H01L21/823468 , H01L27/1052 , H01L27/11573 , H01L29/4234 , H01L29/4983 , H01L29/517 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A method of fabricating a memory device is provided that may begin with forming a layered gate stack atop a semiconductor substrate and patterning a metal electrode layer stopping on the high-k gate dielectric layer of the layered gate stack to provide a first metal gate electrode and a second metal gate electrode on the semiconductor substrate. In a next process sequence, at least one spacer is formed on the first metal gate electrode atop a portion of the high-k gate dielectric layer, wherein a remaining portion of the high-k gate dielectric is exposed. The remaining portion of the high-k gate dielectric layer is etched to provide a first high-k gate dielectric having a portion that extends beyond a sidewall of the first metal gate electrode and a second high-k gate dielectric having an edge that is aligned to a sidewall of the second metal gate electrode.
摘要翻译： 提供一种制造存储器件的方法，其可以开始于在半导体衬底顶上形成分层栅极堆叠并且图案化停止在层状栅叠层的高k栅极电介质层上的金属电极层，以提供第一金属栅电极和 半导体衬底上的第二金属栅电极。 在下一个处理顺序中，在第一金属栅电极的高k栅介质层的一部分顶上形成至少一个间隔物，其中高k栅极电介质的剩余部分被暴露。 蚀刻高k栅极电介质层的剩余部分以提供具有延伸超过第一金属栅电极的侧壁的部分的第一高k栅极电介质和具有对准边缘的第二高k栅极电介质 到第二金属栅电极的侧壁。
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8.发明授权Electrically programmable fuse using anisometric contacts and fabrication method 有权电子可编程保险丝采用不规则接触和制造方法公开(公告)号：US08519507B2
公开(公告)日：2013-08-27
申请号：US12493616
申请日：2009-06-29
IPC分类号： H01L23/52
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.
摘要翻译： 包括阳极接触区域和阴极接触区域的电可编程熔丝由其上形成有硅化物层的多晶硅层和导电连接阴极接触区域与阳极接触区域的熔丝链形成，该熔丝链可通过应用 编程电流，以及分别形成在阴极接触区域的硅化物层上或在阴极接触区域和阳极接触区域的硅化物层上以预定构造形成的多个不规则接触。
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9.发明授权Secure anti-fuse with low voltage programming through localized diffusion heating 有权通过局部扩散加热，通过低电压编程实现安全的反熔丝公开(公告)号：US08350264B2
公开(公告)日：2013-01-08
申请号：US12835764
申请日：2010-07-14
IPC分类号： H01L29/04
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： An antifuse is provided having a unitary monocrystalline semiconductor body including first and second semiconductor regions each having the same first conductivity type, and a third semiconductor region between the first and second semiconductor regions which has a second conductivity type opposite from the first conductivity type. An anode and a cathode can be electrically connected with the first semiconductor region. A conductive region including a metal, a conductive compound of a metal or an alloy of a metal can contact the first semiconductor region and extend between the cathode and the anode. The antifuse can further include a contact electrically connected with the second semiconductor region. In this way, the antifuse can be configured such that the application of a programming voltage between the anode and the cathode heats the first semiconductor region sufficiently to reach a temperature which drives a dopant outwardly therefrom, causing an edge of the first semiconductor region to move closer to an adjacent edge of the second semiconductor region, thus permanently reducing electrical resistance between the first and second semiconductor regions by one or more orders of magnitude.
摘要翻译： 提供一种具有单一单晶半导体本体的反熔丝，该单体半导体本体包括具有相同的第一导电类型的第一和第二半导体区域以及具有与第一导电类型相反的第二导电类型的第一和第二半导体区域之间的第三半导体区域。 阳极和阴极可以与第一半导体区域电连接。 包括金属，金属的导电化合物或金属的合金的导电区域可以接触第一半导体区域并在阴极和阳极之间延伸。 反熔丝还可以包括与第二半导体区域电连接的触点。 以这种方式，反熔丝可被配置为使得在阳极和阴极之间施加编程电压将第一半导体区域充分加热以达到从其向外驱动掺杂剂的温度，从而使第一半导体区域的边缘移动 更靠近第二半导体区域的相邻边缘，从而将第一和第二半导体区域之间的电阻永久地减小一个或多个数量级。
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公开(公告)号：US08004059B2
公开(公告)日：2011-08-23
申请号：US11622616
申请日：2007-01-12
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An eFuse, includes: a substrate and an insulating layer disposed on the substrate; a first layer including a single crystal or polycrystalline silicon disposed on the insulating layer; a second layer including a single crystal or polycrystalline silicon germanium disposed on the first layer, and a third layer including a silicide disposed on the second layer. The Ge has a final concentration in a range of approximately five percent to approximately twenty-five percent.
摘要翻译： eFuse包括：衬底和设置在衬底上的绝缘层; 包括设置在所述绝缘层上的单晶或多晶硅的第一层; 包括设置在第一层上的单晶或多晶硅锗的第二层，以及包括设置在第二层上的硅化物的第三层。 Ge的终浓度范围约为百分之五至百分之二十五。
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