Abstract:
The color shift compensation method comprises: receiving target input gray scale data of a target sub pixel dot in a present line, and acquiring previous output gray scale data of a sub pixel dot of the previous line in the same display data line of the target sub pixel dot, and then, implementing digital to analog conversion to the target output gray scale data of the target sub pixel dot simultaneously corresponding to the target input gray scale data and the previous output gray scale data with combination of the target relationship table to acquire the target voltage of the target sub pixel dot, and ultimately, adjusting a color displayed by a target pixel where the target sub pixel dot is. With the present invention, the color shift issue due to the resistance difference of the fan section can be solved to promote the display effect.
Abstract:
The present invention discloses a driving device and a liquid crystal display. The driving device comprises: a sequence control chip and a data driving chip, and the sequence control chip selectively receives gray scale values of pixel dots, of which an amount is a second value in the gray scale values of pixel dots, of which an amount is a first value, and sends the same to the data driving chip, wherein the data driving chip obtains the gray scale values of the pixel dots, of which the amount is the first value according to the gray scale values of the pixel dots, of which the amount is the second value, and to output the gray scale values of the pixel dots, of which the amount is the first value after interpolation to drive a liquid crystal display.
Abstract:
The present invention provides a multi-phase clock generating circuit and liquid crystal display panel, said circuit comprising: a shift register including N shift registration units, which are cascaded with each other; a first output terminal of nth shift registration units connected to a first input terminal of an (n+1)th shift registration unit; a thin film transistor set including N thin film transistors, said control terminals of said thin film transistors of a nth stage are respectively connected to said first output terminals of (N−n+1) shift registration units.
Abstract:
The present invention provides a multi-phase clock generating circuit and liquid crystal display panel, said circuit comprising: a shift register including N shift registration units, which are cascaded with each other; a first output terminal of nth shift registration units connected to a first input terminal of an (n+1)th shift registration unit; a thin film transistor set including N thin film transistors, said control terminals of said thin film transistors of a nth stage are respectively connected to said first output terminals of (N−n+1) shift registration units.
Abstract:
Disclosed is an adjusting method of a gamma voltage adjusting device. The gamma voltage adjusting device is utilized for providing a liquid crystal panel with N gray levels and includes a printed circuit board assembly and a gamma voltage fine-tuning unit. The adjusting method of the gamma voltage adjusting device includes: generating N+2 gamma voltages with the printed circuit board assembly; inputting the N+2 gamma voltages to the gamma voltage fine-tuning unit; and generating negative polarity driving voltages and positive polarity driving voltages which are symmetrical according to the N+2 gamma voltages. The present invention decreases a number of gamma integrated circuits on the printed circuit board assembly for saving cost by decreasing the 2N gamma voltages in the prior arts to the N+2 gamma voltages.
Abstract:
A liquid crystal (LC) panel includes a plurality of data lines and a plurality of leads connected to the data lines, the driving circuit of the LC panel includes a monitor module and a data-driving module, the data-driving module includes a data latch unit coupled to the lead of the LC panel. The monitor module outputs a time sequence signal to control the data latch unit to output a display signal to the data line. The driving circuit of the LC panel includes a delay unit corresponding to the data line, and the time sequence signal is sent to the data latch unit through the delay unit. When the delay unit reaches a preset delay time, the time sequence signal controls the data latch unit to the display signal to a corresponding data line, and a delay time of a delay unit coupled to a long lead of the LC panel is shorter than a delay time of a delay unit coupled to a short lead of the LC panel.
Abstract:
A liquid crystal display (LCD) panel driver circuit includes a control circuit board, and an LCD panel. The LCD panel includes scan lines and data lines. The control circuit board includes a data driver module that drives the data lines. The LCD panel is configured with a switch module, and the data driver module is coupled to each of the data line via the switch module. The switch module is turned of before a drive of a last line of the scan line ends, and the switch module is turned on when a drive of the next row of the scan line starts.