公开(公告)号：US11442108B1

公开(公告)日：2022-09-13

申请号：US17477237

申请日：2021-09-16

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Gourav Garg ,  Dhulipalla Phaneendra Kumar

IPC: G01R31/3185 ,  G01R31/317

Abstract: A circuit includes: a first power domain including: an isolation cell, a first selection circuit having inputs for receiving a first functional signal and a first test signal and an output for controlling the isolation cell, and a second selection circuit having inputs for receiving a second functional signal and a second test signal and an output coupled to a signal input of the isolation cell; a second power domain including: a first circuit having an input coupled to a signal output of the isolation cell, a first observation element coupled to the signal output of the isolation cell, and a second observation element coupled to an output of the first circuit; where, when in test mode, the first selection circuit controls the isolation cell based on the first test signal, and the second selection circuit provides the second test signal to the signal input of the isolation cell.

公开(公告)号：US11041905B2

公开(公告)日：2021-06-22

申请号：US16671933

申请日：2019-11-01

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

IPC: G01R31/3185 ,  G06F11/267 ,  G06F11/27 ,  G01R31/3183 ,  G01R31/317

Abstract: A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.

公开(公告)号：US10527672B2

公开(公告)日：2020-01-07

申请号：US15713168

申请日：2017-09-22

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/28 ,  H03K19/20

Abstract: Disclosed herein is circuitry for bypassing a medium voltage regulator during testing. The circuitry includes a low voltage regulator to, in operation, generate a first voltage within a first voltage range for powering first circuitry, and a medium voltage regulator to, in operation, generate a second voltage within a second voltage range greater than the first voltage range for powering second circuitry. A low voltage regulator bypass circuit generates a low voltage regulator bypass signal that operates to selectively bypass the low voltage regulator. A medium voltage regulator bypass circuit bypasses the medium voltage regulator as a function of the low voltage regulator bypass signal and an external voltage regulator select signal, the bypass of the medium voltage regulator being such that an external voltage can be applied to the second circuitry.

公开(公告)号：US10393804B2

公开(公告)日：2019-08-27

申请号：US16170479

申请日：2018-10-25

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/3177 ,  G01R31/3193 ,  G06F11/26 ,  G06F11/25 ,  G06F11/27 ,  G01R31/317 ,  G01R31/319

Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

公开(公告)号：US20190094296A1

公开(公告)日：2019-03-28

申请号：US15713168

申请日：2017-09-22

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/28

CPC classification number: G01R31/2896 ,  G01R31/2856 ,  G01R31/2886 ,  H03K19/20

Abstract: Disclosed herein is circuitry for bypassing a medium voltage regulator during testing. The circuitry includes a low voltage regulator to, in operation, generate a first voltage within a first voltage range for powering first circuitry, and a medium voltage regulator to, in operation, generate a second voltage within a second voltage range greater than the first voltage range for powering second circuitry. A low voltage regulator bypass circuit generates a low voltage regulator bypass signal that operates to selectively bypass the low voltage regulator. A medium voltage regulator bypass circuit bypasses the medium voltage regulator as a function of the low voltage regulator bypass signal and an external voltage regulator select signal, the bypass of the medium voltage regulator being such that an external voltage can be applied to the second circuitry.

公开(公告)号：US20190086474A1

公开(公告)日：2019-03-21

申请号：US15710172

申请日：2017-09-20

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: G01R31/327 ,  H03K19/20

Abstract: A method of operating an electronic device during test mode operation of a duplicated voltage monitor includes sensing a functional supply voltage with a voltage monitor, deasserting an output of the voltage monitor if the functional supply voltage is exceeds a threshold, and asserting output of the voltage monitor if the functional supply voltage falls below the threshold. A test supply voltage is sensed with the duplicate voltage monitor, output of the duplicate voltage monitor is deasserted if the test supply voltage exceeds a threshold, and output of the duplicate voltage monitor is asserted if the test supply voltage falls below the threshold. Output of the duplicate voltage monitor is monitored to thereby determine the threshold based upon assertion of the output of the duplicate voltage monitor, and performing a logical operation between outputs of the voltage monitor and the duplicate voltage monitor to generate a power on reset signal.

公开(公告)号：US10228420B2

公开(公告)日：2019-03-12

申请号：US15268848

申请日：2016-09-19

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3193 ,  G06F11/26 ,  G06F11/25 ,  G06F11/27

Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.

公开(公告)号：US10048315B2

公开(公告)日：2018-08-14

申请号：US15203362

申请日：2016-07-06

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185

Abstract: A first clock signal and second clock signal are generated by first and second clock circuits, respectively. A multiplexer selects between the first clock signal and second clock signal to produce a scan clock signal. A non-scan flip flop clocks a data input through to a data output in response to the second clock signal. A scan chain includes a scan flip flop configured to capture the data output from the non-scan flip flop in response to the scan clock signal. The logic state of the captured data in the scan flip flop of the scan chain is indicative of whether the second clock circuit has a stuck-at fault condition (for example, with respect to any one or more included buffer circuits).

公开(公告)号：US20180011141A1

公开(公告)日：2018-01-11

申请号：US15203362

申请日：2016-07-06

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/31723 ,  G01R31/31727 ,  G01R31/31855 ,  G01R31/318552

Abstract: A first clock signal and second clock signal are generated by first and second clock circuits, respectively. A multiplexer selects between the first clock signal and second clock signal to produce a scan clock signal. A non-scan flip flop clocks a data input through to a data output in response to the second clock signal. A scan chain includes a scan flip flop configured to capture the data output from the non-scan flip flop in response to the scan clock signal. The logic state of the captured data in the scan flip flop of the scan chain is indicative of whether the second clock circuit has a stuck-at fault condition (for example, with respect to any one or more included buffer circuits).

公开(公告)号：US09698771B1

公开(公告)日：2017-07-04

申请号：US15203461

申请日：2016-07-06

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: H03K17/22 ,  H03K5/19 ,  H03K19/20

CPC classification number: H03K17/223 ,  G01R31/2832 ,  G06F1/24 ,  G06F1/30 ,  H03K5/19 ,  H03K17/22 ,  H03K19/20

Abstract: A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.