公开(公告)号：US10393804B2

公开(公告)日：2019-08-27

申请号：US16170479

申请日：2018-10-25

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/3177 ,  G01R31/3193 ,  G06F11/26 ,  G06F11/25 ,  G06F11/27 ,  G01R31/317 ,  G01R31/319

Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

公开(公告)号：US10228420B2

公开(公告)日：2019-03-12

申请号：US15268848

申请日：2016-09-19

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3193 ,  G06F11/26 ,  G06F11/25 ,  G06F11/27

Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.

公开(公告)号：US20190064268A1

公开(公告)日：2019-02-28

申请号：US16170479

申请日：2018-10-25

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/317 ,  G01R31/3193 ,  G01R31/3177 ,  G06F11/25 ,  G06F11/26 ,  G06F11/27

CPC classification number: G01R31/31727 ,  G01R31/31722 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31922 ,  G01R31/31937 ,  G06F11/25 ,  G06F11/26 ,  G06F11/27

Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

公开(公告)号：US20180080987A1

公开(公告)日：2018-03-22

申请号：US15268848

申请日：2016-09-19

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/31722 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31937 ,  G06F11/25 ,  G06F11/26 ,  G06F11/27

Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.