公开(公告)号：US20240250668A1

公开(公告)日：2024-07-25

申请号：US18100975

申请日：2023-01-24

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Umesh Chandra Srivastava ,  Shiv Kumar Vats ,  Manish Sharma

IPC: H03K3/037 ,  G01R31/3185 ,  G01R31/3187 ,  H03K19/20

CPC classification number: H03K3/037 ,  G01R31/318597 ,  G01R31/3187 ,  H03K19/20

Abstract: According to an embodiment, a digital circuit includes an OR gate and a flip-flop. The OR gate includes a first input and a second input. The first input of the OR gate is coupled to a control signal, and the second input of the OR gate is coupled to an uncovered functional combination logic of the digital circuit. The first input of the OR gate is configured to be pulled low by the control signal in response to setting the digital circuit in a configuration to test the uncovered functional combination logic. The flip-flop includes a reset pin or a set pin coupled to the output of the OR gate. The output of the flip-flop is configured to be observed during a testing of the uncovered functional combination logic to detect defects in the digital circuit.

公开(公告)号：US11680982B2

公开(公告)日：2023-06-20

申请号：US17510602

申请日：2021-10-26

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma ,  Tripti Gupta

IPC: G01R31/3177 ,  G01R31/317 ,  G06F1/28 ,  G01R31/3185 ,  G06F1/18

CPC classification number: G01R31/3177 ,  G01R31/31721 ,  G06F1/28 ,  G01R31/31723 ,  G01R31/318513 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318558 ,  G01R31/318575 ,  G06F1/18

Abstract: Described herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using a same scan chain compressor-decompressor circuit may be performed. Also disclosed herein are integrated circuit chips having test circuitry designed such that independently selectable testing of different power domains using multiple different scan chain compressor-decompressor circuits may be performed.

公开(公告)号：US20190064270A1

公开(公告)日：2019-02-28

申请号：US15688184

申请日：2017-08-28

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

IPC: G01R31/3185 ,  G06F11/267 ,  G06F11/27 ,  G01R31/3183

Abstract: A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debuging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.

公开(公告)号：US10890619B2

公开(公告)日：2021-01-12

申请号：US16505174

申请日：2019-07-08

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

IPC: G01R31/317 ,  G01R31/3185

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

公开(公告)号：US12146911B1

公开(公告)日：2024-11-19

申请号：US18203345

申请日：2023-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma ,  Jeena Mary George ,  Umesh Chandra Srivastava

IPC: G01R31/3185

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

公开(公告)号：US10386411B2

公开(公告)日：2019-08-20

申请号：US15684334

申请日：2017-08-23

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

IPC: G01R31/317 ,  G01R31/3185

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

公开(公告)号：US20240402249A1

公开(公告)日：2024-12-05

申请号：US18203345

申请日：2023-05-30

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma ,  Jeena Mary George ,  Umesh Chandra Srivastava

IPC: G01R31/3185

Abstract: According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

公开(公告)号：US11041905B2

公开(公告)日：2021-06-22

申请号：US16671933

申请日：2019-11-01

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

IPC: G01R31/3185 ,  G06F11/267 ,  G06F11/27 ,  G01R31/3183 ,  G01R31/317

Abstract: A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.

公开(公告)号：US11714131B1

公开(公告)日：2023-08-01

申请号：US17699900

申请日：2022-03-21

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma ,  Shiv Kumar Vats ,  Umesh Chandra Srivastava

IPC: G01R31/3185 ,  G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/318533 ,  G01R31/318552 ,  G01R31/3177 ,  G01R31/31725

Abstract: In an embodiment, a method for performing scan testing includes: generating first and second scan clock signals; providing the first and second scan clock signals to first and second scan chains, respectively, where the first and second scan clock signals includes respective first shift pulses when a scan enable signal is asserted, and respective first capture pulses when the scan enable signal is deasserted, where the first shift pulse of the first and second scan clock signals correspond to a first clock pulse of a first clock signal, where the first capture pulse of the first scan clock signal corresponds to a second clock pulse of the first clock signal, and where the first capture pulse of the second scan clock signal corresponds to a first clock pulse of a second clock signal different from the first clock signal.

公开(公告)号：US20190064271A1

公开(公告)日：2019-02-28

申请号：US15684334

申请日：2017-08-23

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

IPC: G01R31/3185 ,  G01R31/317

CPC classification number: G01R31/31705 ,  G01R31/318597

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.