公开(公告)号：US11500706B2

公开(公告)日：2022-11-15

申请号：US17233816

申请日：2021-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wandong Kim ,  Jinyoung Kim ,  Sehwan Park ,  Hyun Seo ,  Sangwan Nam

IPC: G11C7/00 ,  G06F11/07 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/34

Abstract: An operating method of a nonvolatile memory device for programming multi-page data, the operating method including: receiving the multi-page data from a memory controller; programming first page data among the multi-page data to first memory cells connected to a word line adjacent to a selected word line; reading previous page data previously stored in second memory cells connected to the selected word line based on a first sensing value and a second sensing value after programming the first page data, calculating a first fail bit number by comparing first bits of the previous page data read based on the first sensing value to second bits of the previous page data read based on the second sensing value; and programming the previous page data read from the second memory cells and second page data among the multi-page data to the second memory cells based on the first fail bit number.

公开(公告)号：US20220028478A1

公开(公告)日：2022-01-27

申请号：US17147851

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan PARK ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C29/50 ,  G11C29/44 ,  G11C7/10 ,  G11C8/18

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US11003393B2

公开(公告)日：2021-05-11

申请号：US16807405

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyeon Shin ,  Sangwan Nam ,  Sangwon Park

IPC: G11C7/00 ,  G06F3/06

Abstract: A method includes performing a first sensing operation to sense write setting data stored in first memory cells of a first memory plane and store first read setting data in a first page buffer circuit of the first memory plane, performing a second sensing operation to sense the write setting data stored in second memory cells of a second memory plane and store second read setting data in a second page buffer circuit of the second memory plane and performing a dump-down operation to store restored setting data corresponding to the write setting data in a buffer based on the first read setting data and the second read setting data.

公开(公告)号：US20210096967A1

公开(公告)日：2021-04-01

申请号：US16865948

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G06F11/20 ,  G11C16/04 ,  G11C16/08

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US20210035650A1

公开(公告)日：2021-02-04

申请号：US17012135

申请日：2020-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiyeon SHIN ,  Sangwan Nam ,  Sangwon Park

IPC: G11C16/34 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  G11C16/10 ,  G11C16/26

Abstract: Method of controlling initialization of nonvolatile memory device, where nonvolatile memory device includes memory cell region including first metal pad and peripheral circuit region including second metal pad and vertically connected to memory cell region by first and second metal pads, includes performing first sensing operation to sense write setting data stored in first memory cells in memory cell region of first memory plane and store first read setting data in first page buffer circuit in peripheral circuit region of first memory plane, performing second sensing operation to sense write setting data stored in second memory cells in memory cell region of second memory plane and store second read setting data in second page buffer circuit in peripheral circuit region of second memory plane and performing dump-down operation to store restored setting data in buffer based on first read setting data and second read setting data.

公开(公告)号：US20200321059A1

公开(公告)日：2020-10-08

申请号：US16825302

申请日：2020-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yongha Park ,  Chaehoon Kim ,  Sangwan Nam

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26 ,  G11C16/30

Abstract: A method controls a memory device that includes a page buffer circuit comprising a plurality of page buffers each comprising at least one latch. The method includes generating by an internal voltage circuit at least one internal voltage among internal voltages used for an operation of the page buffer circuit, the internal voltage circuit providing the at least one internal voltage to the page buffer circuit; and providing to the page buffer circuit a control signal for forming an electrical connection between the internal voltage circuit and a first electrical node of a first page buffer unused for buffering in the page buffer circuit during a set operation for a first latch of a second page buffer.