公开(公告)号：US20210074543A1

公开(公告)日：2021-03-11

申请号：US17012661

申请日：2020-09-04

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Changhyun KIM ,  Sangwoo KIM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Ahrum SOHN ,  Jaehwan JUNG

IPC: H01L21/02 ,  H01L29/66 ,  C23C14/34 ,  C23C14/06 ,  C23C14/58

Abstract: Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: depositing a transition metal dichalcogenide thin film on a substrate; and heat-treating the deposited transition metal dichalcogenide thin film.

公开(公告)号：US20210043452A1

公开(公告)日：2021-02-11

申请号：US16851675

申请日：2020-04-17

Applicant: Samsung Electronics Co., Ltd. ,  RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY

Inventor： Changhyun KIM ,  Sang-Woo KIM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Ahrum SOHN ,  Jaehwan JUNG

IPC: H01L21/02

Abstract: Disclosed herein are a method of forming a transition metal dichalcogenide thin film and a method of manufacturing a device including the same. The method of forming a transition metal dichalcogenide thin film includes: providing a substrate in a reaction chamber; depositing a transition metal dichalcogenide thin film on the substrate using a sputtering process that uses a transition metal precursor and a chalcogen precursor and is performed at a first temperature; and injecting the chalcogen precursor in a gas state and heat-treating the transition metal dichalcogenide thin film at a second temperature that is higher than the first temperature. The substrate may include a sapphire substrate, a silicon oxide (SiO2) substrate, a nanocrystalline graphene substrate, or a molybdenum disulfide (MoS2) substrate.

公开(公告)号：US20200035611A1

公开(公告)日：2020-01-30

申请号：US16215899

申请日：2018-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-Eun Byun ,  Keunwook SHIN ,  Yonghoon KIM ,  Hyeonjin SHIN ,  Hyunjae SONG ,  Changseok LEE ,  Changhyun KIM ,  Yeonchoo CHO

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure includes a dielectric layer including at least one trench, a conductive wiring filling an inside of the at least one trench, and a cap layer on at least one surface of the conductive wiring. The cap layer includes nanocrystalline graphene. The nanocrystalline includes nano-sized crystals.

公开(公告)号：US20170092592A1

公开(公告)日：2017-03-30

申请号：US15083827

申请日：2016-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Hyeonjin SHIN ,  Changhyun KIM ,  Changseok LEE ,  Seongjun PARK ,  Hyunjae SONG

IPC: H01L23/532 ,  H01L23/528

CPC classification number: H01L23/53276 ,  H01L23/485 ,  H01L23/5283

Abstract: A hybrid interconnect structure includes a graphene layer between a non-metallic material layer and a metal layer, and a first interfacial bonding layer between the non-metallic material layer and the graphene layer, or the metal layer and the graphene layer. The graphene layer connects the non-metallic material layer and the metal layer, and the first bonding layer includes a metallic material.