Rule compiler for computer network policy enforcement systems
    41.
    发明授权
    Rule compiler for computer network policy enforcement systems 有权
    计算机网络策略执行系统的规则编译器

    公开(公告)号:US07203744B1

    公开(公告)日:2007-04-10

    申请号:US10264889

    申请日:2002-10-07

    IPC分类号: G06F15/173

    摘要: An integrated policy enforcement system for a computer network implements several policies on the network traffic. A rule compiler compiles these policies and converts them into a rule tree-graph, which is then used to provide desired behavior to the network traffic comprising data packets. The rule compiler comprises three sub-modules namely—a rule input module, a rule tree generator module and a rule output module. The rule input module receives the input for the rule compiler and prepares the input for the rule tree generator module. The rule tree generator module generates the rule tree-graph. The rule tree-graph is a data structure comprising tree data structure and graph data structure. Such a data structure combines the properties of tree data structure and graph data structure, and enhances the performance of the policy enforcement systems by striking a balance between the memory requirement for storing the data structure and the processing capabilities of the system required to process the network traffic. The Output module converts the rule tree-graph to policy files, which can be downloaded to various modules of the policy enforcement systems.

    摘要翻译: 用于计算机网络的综合策略执行系统对网络流量实施若干策略。 规则编译器编译这些策略并将其转换为规则树图,然后将其用于为包含数据包的网络流量提供所需的行为。 规则编译器包括三个子模块,即规则输入模块,规则树生成器模块和规则输出模块。 规则输入模块接收规则编译器的输入,并准备规则树生成器模块的输入。 规则树生成器模块生成规则树形图。 规则树图是包括树数据结构和图形数据结构的数据结构。 这样的数据结构结合了树形数据结构和图形数据结构的特性,通过在存储数据结构的存储器需求和处理网络所需的系统的处理能力之间取得平衡来增强策略执行系统的性能 交通。 输出模块将规则树图转换为策略文件,可将其下载到策略执行系统的各个模块。

    Application processing and decision systems and processes
    42.
    发明申请
    Application processing and decision systems and processes 有权
    应用程序处理和决策系统和流程

    公开(公告)号:US20070022027A1

    公开(公告)日:2007-01-25

    申请号:US10546931

    申请日:2004-08-27

    IPC分类号: G06Q40/00 G06F7/00 G06F17/00

    摘要: The present invention relates to application processing and decisioning systems and processes. One embodiment of the invention includes a method for automating decisioning for a credit request associated with an applicant. The method includes providing a user computer interface adapted to receive information associated with an applicant, and further adapted to display and receive information associated with at least one decision rule. The method also includes receiving information associated with an applicant through the user computer interface; receiving information associated with the applicant from at least one data source; and receiving a selection of information associated with a plurality of decision rules through the user computer interface. Furthermore the method includes receiving a selection of rule flow information associated with the plurality of decision rules through the user computer interface; generating a plurality of decision rules based at least in part on the information associated with the applicant, based at least in part on the information associated with the applicant from at least one data source, and based at least in part on the selection of information associated with a plurality of decision rules, wherein an outcome associated with the at least one decision rule can be obtained; and based in part on at least the rule flow information, displaying at least a portion of the plurality of decision rules through the user computer interface.

    摘要翻译: 本发明涉及应用处理和决策系统和过程。 本发明的一个实施例包括一种用于自动决定与申请人相关联的信用请求的方法。 该方法包括提供适于接收与申请人相关联的信息的用户计算机接口,并且还适于显示和接收与至少一个决策规则相关联的信息。 该方法还包括通过用户计算机接口接收与申请人相关联的信息; 从至少一个数据源接收与申请人相关联的信息; 以及通过所述用户计算机接口接收与多个决策规则相关联的信息的选择。 此外,该方法包括通过用户计算机接口接收与多个决策规则相关联的规则流信息的选择; 至少部分地至少部分地基于与申请人相关联的信息从至少一个数据源生成多个决定规则,至少部分地基于与申请人相关联的信息,并且至少部分地基于与相关联的信息的选择 具有多个决策规则,其中可以获得与所述至少一个决策规则相关联的结果; 并且至少部分地基于规则流信息,通过用户计算机接口显示多个决策规则的至少一部分。

    High-speed track and hold architectures
    43.
    发明申请
    High-speed track and hold architectures 失效
    高速跟踪架构

    公开(公告)号:US20060152393A1

    公开(公告)日:2006-07-13

    申请号:US11284985

    申请日:2005-11-21

    IPC分类号: H03M7/00

    摘要: A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i-1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i-1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.

    摘要翻译: 公开了一种高速采样系统和模数转换器。 对信号进行采样的方法的一个实施例包括接收模拟信号并以F s的速率产生第一采样,并以Fs / N的速率从第一采样产生第二子采样,并具有大约(360 / N)*(i-1)度,其中i从1变化到N.在第一实施例中,至多两个第二子采样器在任何时间点跟踪第一采样器的输出。 在第二实施例中,N个第二子采样器中的仅一个在任何时间点跟踪第一采样器的输出。 第三实施例还包括以Fs / N的速率从第二样本产生第三样本,并且具有近似((360 / N)*(i-1)+180)度的相对相位。 交错模数转换的方法包括接收第三样本的对应的时间交织ADC。

    Gain boosted operational amplifier having a field effect transistor with a well biasing scheme
    45.
    发明申请
    Gain boosted operational amplifier having a field effect transistor with a well biasing scheme 失效
    增益升压运算放大器具有具有阱偏置方案的场效应晶体管

    公开(公告)号:US20050264357A1

    公开(公告)日:2005-12-01

    申请号:US11123121

    申请日:2005-05-06

    申请人: Sandeep Gupta

    发明人: Sandeep Gupta

    IPC分类号: H03F1/30 H03F3/45

    摘要: A biasing scheme for a MOSFET that mitigates the MOSFET body effect. The biasing scheme can be realized replicating the voltage at the source terminal of a MOSFET and applying this replicated voltage to the body terminal. In this manner, the effect of the body transconductance, at high frequencies, becomes a function of the ratio of the well-to-substrate capacitance of the MOSFET to the sum of the well-to-substrate capacitance and the source-to-body capacitance of the transistor. At high frequencies, the biasing scheme mitigates the reduction in gain of a source follower caused by the body effect of a driven MOSFET within the source follower, improves the stability of a feedback network established by a gain boosting amplifier and the driven MOSFET by contributing a negative half plane zero to the transfer function of the feedback network, and reduces the power consumed by the gain boosting amplifier.

    摘要翻译: 用于减轻MOSFET体效应的MOSFET的偏置方案。 偏置方案可以实现复用MOSFET的源极端子处的电压,并将该复制电压施加到主体端子。 以这种方式,在高频下,体导体的影响成为MOSFET的阱间电容与衬底间电容和源对体之和的比值的函数。 晶体管的电容。 在高频时,偏置方案可以减轻由源极跟随器中的驱动MOSFET的体效应导致的源极跟随器增益的降低,从而提高由增益放大器和驱动MOSFET所建立的反馈网络的稳定性, 负半平面零到反馈网络的传递函数,并降低增益放大器消耗的功率。

    Model guided deep learning approach towards prediction of physical system behavior

    公开(公告)号:US11443218B2

    公开(公告)日:2022-09-13

    申请号:US16226461

    申请日:2018-12-19

    摘要: Systems and methods are provided for controlling predictive medical monitoring. A non-linear-predictive-guide model estimates a patient parameter that is used as a guide in a deep neural network for improving accuracy of estimation by the deep neural network. The guide model generates a guiding first estimated patient parameter based on the guide model and patient input data. The deep neural network generates a second estimated patient parameter based on the deep neural network, the patient input data, and the guiding first estimated patient parameter. The deep neural network includes an input layer that receives the guiding first estimated patient parameter, and hidden layers including respective artificial neurons configured to perform a linear or nonlinear transformation on output of at least one artificial neuron from an adjacent layer in the deep neural network. An output layer receives at least one output from a hidden layer.