公开(公告)号：US09508722B2

公开(公告)日：2016-11-29

申请号：US14087005

申请日：2013-11-22

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Xiaomeng Chen ,  Chen-Jong Wang

IPC分类号： H01L29/41 ,  H01L27/108 ,  H01L49/02

CPC分类号： H01L27/10894 ,  H01L21/76877 ,  H01L27/10814 ,  H01L27/1085 ,  H01L27/10897 ,  H01L28/90

摘要： A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

摘要翻译： 半导体装置包括逻辑区和存储区。 存储区具有包括半导体器件的有源区。 存储区域还在有源区域上的一个或多个电介质层内具有电容器，其中电容器在半导体器件上方。 半导体装置还包括至少一个逻辑区域或存储区域内的保护环，并且将逻辑区域与存储区域分开。 电容器在第一电极和第二电极之间具有第一电极，第二电极和绝缘层，其中第一电极基本上大于电容器的其它部分。

公开(公告)号：US20150162329A1

公开(公告)日：2015-06-11

申请号：US14097516

申请日：2013-12-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Ming Chyi Liu

IPC分类号： H01L27/088 ,  H01L21/265 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/762

CPC分类号： H01L27/088 ,  H01L21/28273 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/11521 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883

摘要： A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arraignment includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density.

摘要翻译： 对半导体装置及其形成方法进行说明。 半导体装置包括在有源区的第一侧上的第一栅极结构和在有源区的第二侧上的第二栅极结构，其中第一栅极结构和第二栅极结构共享有源区。 形成半导体检测的方法包括在形成第一栅极结构之前形成有源区的深度注入，然后形成有源区的浅植入物。 在形成第一栅极结构之前形成深度注入减轻了对第一栅极结构劣化的蚀刻工艺的需要。 因此，第一栅极结构具有期望的构造，并且能够形成为更接近其它栅极结构以增强器件密度。

公开(公告)号：US20150097216A1

公开(公告)日：2015-04-09

申请号：US14046987

申请日：2013-10-06

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Xiaomeng Chen ,  Zhiqiang Wu ,  Shih-Chang Liu ,  Chien-Hong Chen

IPC分类号： H01L29/04 ,  H01L21/02

CPC分类号： H01L21/30604 ,  H01L21/3083 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/66537 ,  H01L29/66795 ,  H01L29/7853

摘要： A semiconductor device includes a channel having a first linear surface and a first non-linear surface. The first non-linear surface defines a first external angle of about 80 degrees to about 100 degrees and a second external angle of about 80 degrees to about 100 degrees. The semiconductor device includes a dielectric region covering the channel between a source region and a drain region. The semiconductor device includes a gate electrode covering the dielectric region between the source region and the drain region.

摘要翻译： 半导体器件包括具有第一线性表面和第一非线性表面的通道。 第一非线性表面限定约80度至约100度的第一外角和约80度至约100度的第二外角。 半导体器件包括覆盖源极区域和漏极区域之间的沟道的电介质区域。 半导体器件包括覆盖源极区域和漏极区域之间的电介质区域的栅电极。