公开(公告)号：US20210272964A1

公开(公告)日：2021-09-02

申请号：US17321590

申请日：2021-05-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Chern-Yow Hsu ,  Chen-Jong Wang ,  Chia-Shiung Tsai ,  Shih-Chang Liu ,  Xiaomeng Chen

IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L21/768

摘要： A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.

公开(公告)号：US10269807B2

公开(公告)日：2019-04-23

申请号：US15830060

申请日：2017-12-04

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chern-Yow Hsu ,  Chen-Jong Wang ,  Chia-Shiung Tsai ,  Shih-Chang Liu ,  Xiaomeng Chen

IPC分类号： H01L27/108 ,  H01L49/02 ,  H01L21/311 ,  H01L21/3213

摘要： A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor having a first electrode layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer. At least three dielectric layers are between a bottom surface of the capacitor and the active region.

公开(公告)号：US09978754B2

公开(公告)日：2018-05-22

申请号：US15412115

申请日：2017-01-23

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chern-Yow Hsu ,  Chen-Jong Wang ,  Chia-Shiung Tsai ,  Shih-Chang Liu ,  Xiaomeng Chen

IPC分类号： H01L21/02 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L23/5223 ,  H01L23/585 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

摘要： A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion.

公开(公告)号：US09553096B2

公开(公告)日：2017-01-24

申请号：US14087009

申请日：2013-11-22

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chern-Yow Hsu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Xiaomeng Chen ,  Chen-Jong Wang

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L23/58 ,  H01L49/02 ,  H01L23/522

CPC分类号： H01L27/10894 ,  H01L23/5223 ,  H01L23/585 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/10897 ,  H01L28/87 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/00

摘要： A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region. The semiconductor arrangement includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where an electrode unit of the first electrode has a first portion and a second portion, and where the second portion is above the first portion and is wider than the first portion.

摘要翻译： 半导体装置包括逻辑区和存储区。 存储区具有包括半导体器件的有源区。 存储区域还在活性区域上的一个或多个电介质层内具有电容器。 半导体装置包括至少一个逻辑区域或存储区域内的保护环，并且将逻辑区域与存储区域分开。 电容器在第一电极和第二电极之间具有第一电极，第二电极和绝缘层，其中第一电极的电极单元具有第一部分和第二部分，并且其中第二部分在第一部分之上 并且比第一部分宽。

公开(公告)号：US20160204200A1

公开(公告)日：2016-07-14

申请号：US15077097

申请日：2016-03-22

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Xiaomeng Chen ,  Chien-Hong Chen ,  Shih-Chang Liu ,  Zhiqiang Wu

IPC分类号： H01L29/10 ,  H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L29/1033 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel. The semiconductor device includes a second channel having a third linear surface and a third non-linear surface. The semiconductor device includes a second dielectric region surrounding the second channel. The semiconductor device includes a gate electrode surrounding the first dielectric region and the second dielectric region.

公开(公告)号：US09299784B2

公开(公告)日：2016-03-29

申请号：US14046985

申请日：2013-10-06

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Xiaomeng Chen ,  Zhiqiang Wu ,  Shih-Chang Liu ,  Chien-Hong Chen

IPC分类号： H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L29/1033 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/66787 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： A semiconductor device includes a first channel having a first linear surface and a first non-linear surface. The semiconductor device includes a first dielectric region surrounding the first channel. The semiconductor device includes a second channel having a third linear surface and a third non-linear surface. The semiconductor device includes a second dielectric region surrounding the second channel. The semiconductor device includes a gate electrode surrounding the first dielectric region and the second dielectric region.

摘要翻译： 半导体器件包括具有第一线性表面和第一非线性表面的第一通道。 半导体器件包括围绕第一通道的第一电介质区域。 半导体器件包括具有第三线性表面和第三非线性表面的第二通道。 半导体器件包括围绕第二通道的第二电介质区域。 半导体器件包括围绕第一电介质区域和第二电介质区域的栅电极。

公开(公告)号：US20150187777A1

公开(公告)日：2015-07-02

申请号：US14144676

申请日：2013-12-31

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chern-Yow Hsu ,  Ming Chyi Liu ,  Shih-Chang Liu ,  Chia-Shiung Tsai ,  Xiaomeng Chen ,  Chen-Jong Wang

IPC分类号： H01L27/108

CPC分类号： H01L27/10814 ,  H01L27/10852 ,  H01L28/90

摘要： A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor includes a first electrode over at least one dielectric layer over the active region. The first electrode surrounds an open space within the capacitor. The first electrode has a non-linear first electrode sidewall.

摘要翻译： 半导体装置包括包括半导体器件的有源区。 半导体装置包括电容器。 电容器包括位于有源区上的至少一个电介质层上的第一电极。 第一电极围绕电容器内的开放空间。 第一电极具有非线性第一电极侧壁。

公开(公告)号：US20140110823A1

公开(公告)日：2014-04-24

申请号：US13659219

申请日：2012-10-24

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chung-Yen Chou ,  Po-ken Lin ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L29/945

摘要： One or more techniques or systems for forming a contact structure for a deep trench capacitor (DTC) are provided herein. In some embodiments, a contact structure includes a substrate region, a first region, a second region, contact landings, a first trench region, a first landing region, and a second trench region. In some embodiments, a first region is over the substrate region and a second region is over the first region. For example, the first region and the second region are in the first trench region or the second trench region. Additionally, a contact landing over the first trench region, the second trench region, or the first landing region is in contact with the first region, the second region, or the substrate region. In this manner, additional contacts are provided and landing area is reduced, thus reducing resistance of the DTC, for example.

摘要翻译： 本文提供了用于形成深沟槽电容器（DTC）的接触结构的一种或多种技术或系统。 在一些实施例中，接触结构包括基底区域，第一区域，第二区域，接触平台，第一沟槽区域，第一着陆区域和第二沟槽区域。 在一些实施例中，第一区域在衬底区域上方，第二区域在第一区域之上。 例如，第一区域和第二区域在第一沟槽区域或第二沟槽区域中。 此外，在第一沟槽区域，第二沟槽区域或第一着陆区域上的接触着接触与第一区域，第二区域或衬底区域接触。 以这种方式，提供额外的触点并降低着陆面积，从而降低DTC的阻力。

公开(公告)号：US12068313B2

公开(公告)日：2024-08-20

申请号：US16995538

申请日：2020-08-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Harry-Hak-Lay Chuang ,  Wei Cheng Wu ,  Shih-Chang Liu ,  Ming Chyi Liu

IPC分类号： H01L27/088 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/11521 ,  H01L29/66 ,  H01L29/788 ,  H10B41/30

CPC分类号： H01L27/088 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823481 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7883 ,  H10B41/30 ,  H01L29/6656

摘要： A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an active area and a second gate structure on a second side of the active area, where the first gate structure and the second gate structure share the active area. A method of forming the semiconductor arrangement includes forming a deep implant of the active area before forming the first gate structure, and then forming a shallow implant of the active area. Forming the deep implant prior to forming the first gate structure alleviates the need for an etching process that degrades the first gate structure. The first gate structure thus has a desired configuration and is able to be formed closer to other gate structures to enhance device density.

公开(公告)号：US11856750B2

公开(公告)日：2023-12-26

申请号：US17321590

申请日：2021-05-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

发明人： Chern-Yow Hsu ,  Chen-Jong Wang ,  Chia-Shiung Tsai ,  Shih-Chang Liu ,  Xiaomeng Chen

IPC分类号： H10B12/00 ,  H01L49/02 ,  H01L21/768

CPC分类号： H10B12/09 ,  H01L21/76877 ,  H01L28/90 ,  H10B12/315 ,  H10B12/50 ,  H10B12/03

摘要： A semiconductor arrangement includes a logic region and a memory region. The memory region has an active region that includes a semiconductor device. The memory region also has a capacitor within one or more dielectric layers over the active region, where the capacitor is over the semiconductor device. The semiconductor arrangement also includes a protective ring within at least one of the logic region or the memory region and that separates the logic region from the memory region. The capacitor has a first electrode, a second electrode and an insulating layer between the first electrode and the second electrode, where the first electrode is substantially larger than other portions of the capacitor.