公开(公告)号：US20220075626A1

公开(公告)日：2022-03-10

申请号：US17528403

申请日：2021-11-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Horst Diewald ,  Johann Zipperer

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/30

Abstract: A processor includes a plurality of execution units. At least one of the execution units is configured to determine, based on a field of a first instruction, a number of additional instructions to execute in conjunction with the first instruction and prior to execution of the first instruction.

公开(公告)号：US11231933B2

公开(公告)日：2022-01-25

申请号：US16843998

申请日：2020-04-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Johann Zipperer

IPC: G06F9/38 ,  G06F9/30

Abstract: A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the execution pipeline. The maximum number is based on a value contained in a pre-fetch threshold field of an instruction executed in the execution pipeline.

公开(公告)号：US20210172984A1

公开(公告)日：2021-06-10

申请号：US17181166

申请日：2021-02-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Horst Diewald ,  Johann Zipperer ,  Peter Weber ,  Anton Brauchle

IPC: G01R21/127 ,  G01R15/18

Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.

公开(公告)号：US20200334197A1

公开(公告)日：2020-10-22

申请号：US16920901

申请日：2020-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

公开(公告)号：US10802058B2

公开(公告)日：2020-10-13

申请号：US15889010

申请日：2018-02-05

Applicant: Texas Instruments Incorporated

Inventor： Horst Diewald ,  Johann Zipperer ,  Peter Weber ,  Anton Brauchle

IPC: G01R21/00 ,  G01R21/06 ,  G01R22/10 ,  G01R15/00

Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.

公开(公告)号：US20200301709A1

公开(公告)日：2020-09-24

申请号：US16843998

申请日：2020-04-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Christian Wiencke ,  Johann Zipperer

IPC: G06F9/38 ,  G06F9/30

Abstract: A method and apparatus for controlling pre-fetching in a processor. A processor includes an execution pipeline and an instruction pre-fetch unit. The execution pipeline is configured to execute instructions. The instruction pre-fetch unit is coupled to the execution pipeline. The instruction pre-fetch unit includes instruction storage to store pre-fetched instructions, and pre-fetch control logic. The pre-fetch control logic is configured to fetch instructions from memory and store the fetched instructions in the instruction storage. The pre-fetch control logic is also configured to provide instructions stored in the instruction storage to the execution pipeline for execution. The pre-fetch control logic is further configured set a maximum number of instruction words to be pre-fetched for execution subsequent to execution of an instruction currently being executed in the instruction pipeline. The maximum number is based on a value contained in a pre-fetch threshold field of an instruction executed in the execution pipeline.

公开(公告)号：US20190257863A1

公开(公告)日：2019-08-22

申请号：US16402370

申请日：2019-05-03

Applicant: Texas Instruments Incorporated

Inventor： Horst Diewald ,  Johann Zipperer ,  Peter Weber ,  Anton Brauchle

IPC: G01R21/00 ,  G06F1/28 ,  G06F1/26

Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant ON-time.

公开(公告)号：US10037287B2

公开(公告)日：2018-07-31

申请号：US15600815

申请日：2017-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Johann Zipperer

IPC: G06F12/14 ,  G06F21/53

CPC classification number: G06F12/1425 ,  G06F21/53

Abstract: A method of protecting software for embedded applications against unauthorized access. Software to be protected is loaded into a protected memory area. Access to the protected memory area is controlled by sentinel logic circuitry. The sentinel logic circuitry allows access to the protected memory area from only either within the protected memory area or from outside of the protected memory area but through a dedicated memory location within the protected memory area. The dedicated memory location then points to protected address locations within the protected memory area.

公开(公告)号：US20180018298A1

公开(公告)日：2018-01-18

申请号：US15714212

申请日：2017-09-25

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS DEUTSCHLAND GMBH

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

公开(公告)号：US20160292127A1

公开(公告)日：2016-10-06

申请号：US14678939

申请日：2015-04-04

Applicant: Texas Instruments Incorporated ,  Texas Instruments Deutschland, GMBH

Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

IPC: G06F15/80

CPC classification number: G06F15/80 ,  G06F9/30014 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/325 ,  G06F9/3822 ,  G06F9/3853 ,  G06F9/3877

Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

Abstract translation: 具有短并行指令字的低能量加速器处理器架构的方法和装置。 集成电路包括具有数据宽度N的系统总线，其中N是正整数; 耦合到所述系统总线并被配置为执行从耦合到所述系统总线的存储器检索的指令的中央处理器单元; 以及耦合到所述系统总线并被配置为执行从低能量加速器代码存储器检索的指令字的低能量加速器处理器，所述低能量加速器处理器具有多个执行单元，所述执行单元包括加载存储单元，负载系数单元，乘法 单元和蝶形/加法器ALU单元，每个执行单元被配置为响应于从检索到的指令字解码的操作码执行操作，其中指令字的宽度等于数据宽度N.附加方法和装置 被披露。