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    Low energy accelerator processor architecture with short parallel instruction word
    1.
    发明授权
    Low energy accelerator processor architecture with short parallel instruction word 有权

    公开(公告)号：US10740280B2

    公开(公告)日：2020-08-11

    申请号：US15714212

    申请日：2017-09-25

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

    IPC: G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

    Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

    Computer and methods for solving math functions
    3.
    发明授权
    Computer and methods for solving math functions 有权

    公开(公告)号：US10430494B2

    公开(公告)日：2019-10-01

    申请号：US15426277

    申请日：2017-02-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kyong Ho Lee ,  Seok-Jun Lee ,  Manish Goel

    IPC: G06F17/17 ,  G06F9/30 ,  G06F7/544 ,  G06F7/483

    Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.

    Computer and Methods for Solving Math Functions
    4.
    发明申请
    Computer and Methods for Solving Math Functions 审中-公开

    公开(公告)号：US20170147532A1

    公开(公告)日：2017-05-25

    申请号：US15426277

    申请日：2017-02-07

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Kyong Ho Lee ,  Seok-Jun Lee ,  Manish Goel

    IPC: G06F17/17 ,  G06F7/483

    CPC classification number: G06F17/17 ,  G06F7/483 ,  G06F7/544 ,  G06F9/3001

    Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.

    Computer and methods for solving math functions
    5.
    发明授权
    Computer and methods for solving math functions 有权

    公开(公告)号：US09606796B2

    公开(公告)日：2017-03-28

    申请号：US14067343

    申请日：2013-10-30

    Applicant: Texas Instruments Incorporated

    Inventor： Kyong Ho Lee ,  Seok-Jun Lee ,  Manish Goel

    IPC: G06F9/54 ,  G06F9/30

    CPC classification number: G06F17/17 ,  G06F7/483 ,  G06F7/544 ,  G06F9/3001

    Abstract: Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The operations level performs mathematical operations. The driver level includes a first lookup table and a second lookup table, wherein the first lookup table includes first data for calculating at least one mathematical function using a first level of accuracy. The second lookup table includes second data for calculating the at least one mathematical function using a second level of accuracy, wherein the first level of accuracy is greater than the second level of accuracy. A driver executes either the first data or the second data depending on a selected level of accuracy.

    LOAD STORE CIRCUIT WITH DEDICATED SINGLE OR DUAL BIT SHIFT CIRCUIT AND OPCODES FOR LOW POWER ACCELERATOR PROCESSOR
    6.
    发明申请
    LOAD STORE CIRCUIT WITH DEDICATED SINGLE OR DUAL BIT SHIFT CIRCUIT AND OPCODES FOR LOW POWER ACCELERATOR PROCESSOR 审中-公开
    具有专用单个或双位移位电路的负载存储电路和低功率加速器处理器的操作码

    公开(公告)号：US20170060586A1

    公开(公告)日：2017-03-02

    申请号：US14840308

    申请日：2015-08-31

    Applicant: Texas Instruments Incorporated

    Inventor： Srinivas Lingam ,  Seok-Jun Lee

    IPC: G06F9/30 ,  G06F13/40

    CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F13/4068 ,  Y02D10/14 ,  Y02D10/151

    Abstract: Described examples include integrated circuits such as microcontrollers with a low energy accelerator processor circuit or other application specific integrated processor circuit including a load store circuit operative to perform load and store operations associated with at least one register and a low gate count shift circuit to selectively shift the data of the register by only an integer number bits less than the register data width without using a barrel shifter for low power operation to support vector operations for FFT or filtering functions.

    Abstract translation: 所描述的示例包括诸如具有低能量加速器处理器电路的微控制器或其他专用集成处理器电路的集成电路，其包括可操作以执行与至少一个寄存器和低门限值移位电路相关联的负载和存储操作的负载存储电路，以选择性地移位 寄存器的数据只有一个整数比特位数小于寄存器数据宽度，而不使用桶形移位器进行低功耗操作，以支持FFT或滤波功能的向量运算。

    Low Energy Accelerator Processor Architecture with Short Parallel Instruction Word
    9.
    发明申请
    Low Energy Accelerator Processor Architecture with Short Parallel Instruction Word 审中-公开

    公开(公告)号：US20200334197A1

    公开(公告)日：2020-10-22

    申请号：US16920901

    申请日：2020-07-06

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Srinivas Lingam ,  Seok-Jun Lee ,  Johann Zipperer ,  Manish Goel

    IPC: G06F15/80 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38

    Abstract: Methods and apparatus for a low energy accelerator processor architecture with short parallel instruction word. An integrated circuit includes a system bus having a data width N, where N is a positive integer; a central processor unit coupled to the system bus and configured to execute instructions retrieved from a memory coupled to the system bus; and a low energy accelerator processor coupled to the system bus and configured to execute instruction words retrieved from a low energy accelerator code memory, the low energy accelerator processor having a plurality of execution units including a load store unit, a load coefficient unit, a multiply unit, and a butterfly/adder ALU unit, each of the execution units configured to perform operations responsive to op-codes decoded from the retrieved instruction words, wherein the width of the instruction words is equal to the data width N. Additional methods and apparatus are disclosed.

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