公开(公告)号：US10748899B2

公开(公告)日：2020-08-18

申请号：US15715541

申请日：2017-09-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/06

Abstract: An integrated circuit having an epitaxial source and drain, which reduces gate burnout and increases switching speed so that is suitable for high voltage applications, is provided. The integrated circuit includes a semiconductor substrate having a high voltage N-well (HVNW) and a high voltage P-well (HVPW). The integrated circuit further includes a high-voltage device on the semiconductor substrate. The high-voltage device includes an epitaxial p-type source disposed in the HVNW, an epitaxial p-type drain disposed in the HVPW, and a gate arranged between the epitaxial p-type source and the epitaxial p-type drain on a surface of the semiconductor substrate.

公开(公告)号：US10553583B2

公开(公告)日：2020-02-04

申请号：US15688276

申请日：2017-08-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region, and a method of formation. In some embodiments, the integrated circuit comprises a first gate boundary dielectric layer disposed over a substrate in the low voltage region. A second gate boundary dielectric layer is disposed over the substrate in the high voltage region having a thickness greater than that of the first boundary dielectric layer. The first boundary dielectric layer meets the second boundary dielectric layer at the boundary region. A first polysilicon component is disposed within the boundary region over the first boundary dielectric layer and the second gate boundary layer. A second polysilicon component is disposed within the boundary region over the first polysilicon component. A hard mask component is disposed over the first polysilicon component and laterally neighbored to the second polysilicon component.

公开(公告)号：US20200027845A1

公开(公告)日：2020-01-23

申请号：US16587819

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei ,  Meng-Han Lin

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/10 ,  H01L29/735 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08

Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.

公开(公告)号：US09502585B2

公开(公告)日：2016-11-22

申请号：US14690209

申请日：2015-04-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Han Lin ,  Chien-Chih Chou ,  Chih-Wen Hsiung ,  Kong-Beng Thei

IPC: H01L29/872 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/324 ,  H01L29/06 ,  H01L29/47 ,  H01L21/225

CPC classification number: H01L29/872 ,  H01L21/2253 ,  H01L21/2255 ,  H01L21/26513 ,  H01L21/28518 ,  H01L21/3115 ,  H01L21/762 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/66143

Abstract: A method of manufacturing a Schottky barrier diode is provided, which includes: providing a semiconductor substrate including a first well region of a first conductivity type in the semiconductor substrate; forming a surface-doped layer having a dopant of a second conductivity type opposite to the first conductivity type in the first well region; forming a dielectric layer in contact with the surface-doped layer; performing a thermal treatment on the surface-doped layer to move the dopant of the surface-doped layer in the dielectric layer; removing the dielectric layer to expose the first well region; and forming a silicide layer in contact with the exposed first well region. A Schottky barrier diode is also provided.

Abstract translation: 提供一种制造肖特基势垒二极管的方法，其包括：在半导体衬底中提供包括第一导电类型的第一阱区的半导体衬底; 在所述第一阱区中形成具有与所述第一导电类型相反的第二导电类型的掺杂剂的表面掺杂层; 形成与表面掺杂层接触的介电层; 对所述表面掺杂层进行热处理，以移动所述介电层中的所述表面掺杂层的掺杂剂; 去除介电层以露出第一阱区; 以及形成与暴露的第一阱区域接触的硅化物层。 还提供肖特基势垒二极管。