公开(公告)号：US11469307B2

公开(公告)日：2022-10-11

申请号：US17098867

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Kong-Beng Thei ,  Chien-Chih Chou ,  Alexander Kalnitsky ,  Szu-Hsien Liu ,  Huan-Chih Yuan

IPC: H01L29/423 ,  H01L29/40 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/78

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

公开(公告)号：US20220102518A1

公开(公告)日：2022-03-31

申请号：US17098867

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Kong-Beng Thei ,  Chien-Chih Chou ,  Alexander Kalnitsky ,  Szu-Hsien Liu ,  Huan-Chih Yuan

IPC: H01L29/423 ,  H01L21/762 ,  H01L29/40

Abstract: In some embodiments, the present disclosure relates to a semiconductor device that includes a well region with a substrate. A source region and a drain region are arranged within the substrate on opposite sides of the well region. A gate electrode is arranged over the well region, has a bottom surface arranged below a topmost surface of the substrate, and extends between the source and drain regions. A trench isolation structure surrounds the source region, the drain region, and the gate electrode. A gate dielectric structure separates the gate electrode from the well region, the source, region, the drain region, and the trench isolation structure. The gate electrode structure has a central portion and a corner portion. The central portion has a first thickness, and the corner portion has a second thickness that is greater than the first thickness.

公开(公告)号：US20210273069A1

公开(公告)日：2021-09-02

申请号：US16929640

申请日：2020-07-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Liang Chu ,  Chien-Chih Chou ,  Chih-Chang Cheng ,  Yi-Huan Chen ,  Kong-Beng Thei ,  Ming-Ta Lei ,  Ruey-Hsin Liu ,  Ta-Yuan Kung

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/49 ,  H01L29/45 ,  H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/762 ,  H01L29/66

Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.

公开(公告)号：US20200051975A1

公开(公告)日：2020-02-13

申请号：US16656756

申请日：2019-10-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Fu-Jier Fan ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky ,  Yi-Sheng Chen

IPC: H01L27/088 ,  H01L21/8238 ,  H01L29/51 ,  H01L27/092 ,  H01L27/02 ,  H01L27/04 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/423

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a low voltage transistor device is disposed in a low voltage region defined on a substrate. The low voltage transistor device comprises a low voltage gate electrode and a first gate dielectric separating the low voltage gate electrode from the substrate. A high voltage transistor device is disposed in a high voltage region defined on the substrate. The high voltage transistor device comprises a high voltage gate electrode and a high voltage gate dielectric separating the high voltage gate electrode from the substrate. A first interlayer dielectric layer is disposed over the substrate surrounding the low voltage transistor device and the high voltage transistor device. The high voltage gate electrode is disposed on the first interlayer dielectric layer and separated from the substrate by the first interlayer dielectric layer.

公开(公告)号：US10535752B2

公开(公告)日：2020-01-14

申请号：US15992817

申请日：2018-05-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kong-Beng Thei ,  Chien-Chih Chou ,  Hsiao-Chin Tuan ,  Yi-Huan Chen ,  Alexander Kalnitsky

IPC: H01L29/66 ,  H01L21/768 ,  H01L29/78

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes a pair of source/drain regions disposed in a semiconductor substrate, where the source/drain regions are laterally spaced. A gate electrode is disposed over the semiconductor substrate between the source/drain regions. Sidewall spacers are disposed over the semiconductor substrate on opposite sides of the gate electrode. A silicide blocking structure is disposed over the sidewalls spacers, where respective sides of the source/drain regions facing the gate electrode are spaced apart from outer sides of the sidewall spacers and are substantially aligned with outer sidewalls of the silicide blocking structure.

公开(公告)号：US10516029B2

公开(公告)日：2019-12-24

申请号：US16437137

申请日：2019-06-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Fu-Jier Fan ,  Kong-Beng Thei ,  Yi-Sheng Chen ,  Szu-Hsien Liu

IPC: H01L29/49 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/762

Abstract: In some embodiments, an integrated circuit is provided. The integrated circuit may include an inner ring-shaped isolation structure that is disposed in a semiconductor substrate. Further, the inner-ring shaped isolation structure may demarcate a device region. An inner ring-shaped well is disposed in the semiconductor substrate and surrounds the inner ring-shaped isolation structure. A plurality of dummy gates are arranged over the inner ring-shaped well. Moreover, the plurality of dummy gates are arranged within an interlayer dielectric layer.

公开(公告)号：US10263064B2

公开(公告)日：2019-04-16

申请号：US15638387

申请日：2017-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Yu Ku ,  Chien-Chih Chou ,  Chen-Shien Chen ,  Hon-Lin Huang ,  Chi-Cheng Chen ,  Kuang-Yi Wu

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/00

Abstract: Semiconductor devices and methods of forming the same are disclosed. One of the semiconductor device includes an inductor structure, and the inductor structure is on a substrate and includes a first metal layer, a magnetic stack, a polymer layer and a second metal layer. The first metal layer is over the substrate. The magnetic stack is over the first metal layer and has a substantially zigzag shaped sidewall. The polymer layer is over the first metal layer and encapsulates the magnetic stack. The second metal layer is over the polymer layer.

公开(公告)号：US11410999B2

公开(公告)日：2022-08-09

申请号：US16797334

申请日：2020-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Alexander Kalnitsky ,  Kong-Beng Thei ,  Ming Chyi Liu ,  Shih-Chung Hsiao ,  Jhih-Bin Chen

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/51 ,  H01P1/15 ,  H01L23/48

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

公开(公告)号：US11133226B2

公开(公告)日：2021-09-28

申请号：US16169220

申请日：2018-10-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Ta-Wei Lin ,  Hsiao-Chin Tuan ,  Alexander Kalnitsky ,  Kong-Beng Thei ,  Chia-Hong Wu

IPC: H01L29/49 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/51 ,  H01L21/3105 ,  H01L29/08 ,  H01L27/092 ,  H01L29/45

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a fully silicided (FUSI) gated device, the method including: forming a masking layer onto a gate structure over a substrate, the gate structure comprising a polysilicon layer. Forming a first source region and a first drain region on opposing sides of the gate structure within the substrate, the gate structure is formed before the first source and drain regions. Performing a first removal process to remove a portion of the masking layer and expose an upper surface of the polysilicon layer. The first source and drain regions are formed before the first removal process. Forming a conductive layer directly contacting the upper surface of the polysilicon layer. The conductive layer is formed after the first removal process. Converting the conductive layer and polysilicon layer into a FUSI layer. The FUSI layer is thin and uniform in thickness.

公开(公告)号：US10804220B2

公开(公告)日：2020-10-13

申请号：US16587867

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Kong-Beng Thei ,  Meng-Han Lin

IPC: H01L23/00 ,  H01L29/735 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10

Abstract: In some embodiments, a bipolar junction transistor (BJT) is provided. The BJT may include a collector region that is disposed within a semiconductor substrate. A base region that is disposed within the semiconductor substrate and arranged within the collector region. An emitter region that is disposed within the semiconductor substrate and arranged within the base region. A pre-metal dielectric layer that is disposed over an upper surface of the semiconductor substrate and that separates the upper surface of the semiconductor substrate from a lowermost metal interconnect layer. A first plurality of dishing prevention columns that are arranged over the emitter region and within the pre-metal dielectric layer, where the plurality of dishing prevention columns each include a dummy gate that is conductive and electrically floating.