公开(公告)号：US20220068862A1

公开(公告)日：2022-03-03

申请号：US17002471

申请日：2020-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/498

Abstract: Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.

公开(公告)号：US20210351076A1

公开(公告)日：2021-11-11

申请号：US17379775

申请日：2021-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Kuo-Chung Yee ,  Mirng-Ji Lii ,  Chien-Hsun Lee ,  Jiun Yi Wu

IPC: H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10

Abstract: An embodiment is a package including a first package component. The first package component including a first die attached to a first side of a first interconnect structure, a molding material surrounding the first die, and a second interconnect structure over the molding material and the first die, a first side of the second interconnect structure coupled to the first die with first electrical connectors. The first package component further includes a plurality of through molding vias (TMVs) extending through the molding material, the plurality of TMVs coupling the first interconnect structure to the second interconnect structure, and a second die attached to a second side of the second interconnect structure with second electrical connectors, the second side of the second interconnect structure being opposite the first side of the second interconnect structure.

公开(公告)号：US20250079368A1

公开(公告)日：2025-03-06

申请号：US18951773

申请日：2024-11-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.

公开(公告)号：US12243843B2

公开(公告)日：2025-03-04

申请号：US17813639

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  G02B6/42 ,  H01L23/13 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00 ,  H01L25/10

Abstract: A package includes a package substrate including an insulating layer having a trench and a package component bonded to the package substrate. The package component includes a redistribution structure, an optical die bonded to the redistribution structure, the optical die including an edge coupler near a first sidewall of the optical die, a dam structure on the redistribution structure near the first sidewall of the optical die, a first underfill between the optical die and the redistribution structure, an encapsulant encapsulating the optical die, and an optical glue in physical contact with the first sidewall of the optical die. The first underfill does not extend along the first sidewall of the optical die. The optical glue separates the dam structure from the encapsulant. The package further includes a second underfill between the insulating layer and the package component. The second underfill is partially disposed in the trench.

公开(公告)号：US12199080B2

公开(公告)日：2025-01-14

申请号：US18302165

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Chien-Hsun Lee ,  Jiun Yi Wu

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

Abstract: A method includes bonding a first package to a second package to form a third package. The first package is an Integrated Fan-Out (InFO) package including a plurality of package components, and an encapsulating material encapsulating the plurality of package components therein. The plurality of package components include device dies. The method further includes placing at least a portion of the third package into a recess in a Printed Circuit Board (PCB). The recess extends from a top surface of the PCB to an intermediate level between the top surface and a bottom surface of the PCB. Wire bonding is performed to electrically connect the third package to the PCB.

公开(公告)号：US12183700B2

公开(公告)日：2024-12-31

申请号：US17874402

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: Semiconductor devices and methods of manufacture are described herein. The methods include forming a local organic interconnect (LOI) by forming a stack of conductive traces embedded in a passivation material, forming first and second local contacts over the passivation material, the second local contact being electrically coupled to the first local contact by a first conductive trace of the stack. The methods further include forming a backside redistribution layer (RDL) and a front side RDL on opposite sides of the LOI with TMVs electrically coupling the backside and front side RDLs to one another. First and second external contacts are formed over the backside RDL for mounting of semiconductor devices, the first and second external contacts being electrically connected to one another by the LOI. An interconnect structure is attached to the front side RDL for further routing. External connectors electrically coupled to the external contacts at the backside RDL.

公开(公告)号：US20240395685A1

公开(公告)日：2024-11-28

申请号：US18790524

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48

Abstract: An integrated circuit package that includes symmetrical redistribution structures on either side of a core substrate is provided. In an embodiment, a device comprises a core substrate, a first redistribution structure comprising one or more layers, a second redistribution comprising one or more layers, a first integrated circuit die, and a set of external conductive features. The core substrate is disposed between the first redistribution structure and the second redistribution structure, the first integrated circuit die is disposed on the first distribution structure on the opposite side from the core substrate; and the set of external conductive features are disposed on a side of the second redistribution structure opposite the core substrate. The first redistribution structure and second redistribution structure have symmetrical redistribution layers to each other with respect to the core substrate.

公开(公告)号：US20240387343A1

公开(公告)日：2024-11-21

申请号：US18789255

申请日：2024-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/14 ,  H01L23/29 ,  H01L23/31

Abstract: A semiconductor package includes an interconnect structure including a redistribution structure, an insulating layer over the redistribution structure, and conductive pillars on the insulating layer, wherein the conductive pillars are connected to the redistribution structure, wherein the interconnect structure is free of active devices, a routing substrate including a routing layer over a core substrate, wherein the interconnect structure is bonded to the routing substrate by solder joints, wherein each of the solder joints bonds a conductive pillar of the conductive pillars to the routing layer, an underfill surrounding the conductive pillars and the solder joints, and a semiconductor device including a semiconductor die connected to a routing structure, wherein the routing structure is bonded to an opposite side of the interconnect structure as the routing substrate.

公开(公告)号：US12142560B2

公开(公告)日：2024-11-12

申请号：US17408840

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shi Liu ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Hao-Cheng Hou ,  Hung-Jen Lin ,  Jung Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Li-Wei Chou

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

公开(公告)号：US20240371791A1

公开(公告)日：2024-11-07

申请号：US18770750

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jiun Yi Wu ,  Chen-Hua Yu

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538

Abstract: A device includes an interconnect device attached to a redistribution structure, wherein the interconnect device includes conductive routing connected to conductive connectors disposed on a first side of the interconnect device, a molding material at least laterally surrounding the interconnect device, a metallization pattern over the molding material and the first side of the interconnect device, wherein the metallization pattern is electrically connected to the conductive connectors, first external connectors connected to the metallization pattern, and semiconductor devices connected to the first external connectors.