公开(公告)号：US20250125224A1

公开(公告)日：2025-04-17

申请号：US18442677

申请日：2024-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yao-Cheng Wu ,  Hua-Kai Lin ,  Hao-Cheng Hou ,  Tsung-Ding Wang ,  Hao-Yi Tsai

IPC: H01L23/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/538

Abstract: In an embodiment, a device includes: an interposer including: a back-side redistribution structure; an interconnection die over the back-side redistribution structure, the interconnection die including a substrate, a through-substrate via protruding from the substrate, and an isolation layer around the through-substrate via; a first encapsulant around the interconnection die, a surface of the first encapsulant being substantially coplanar with a surface of the isolation layer and a surface of the through-substrate via; and a front-side redistribution structure over the first encapsulant, the front-side redistribution structure including a first conductive via that physically contacts the through-substrate via, the isolation layer separating the first conductive via from the substrate.

公开(公告)号：US20230307375A1

公开(公告)日：2023-09-28

申请号：US18151583

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Cheng Hou ,  Tsung-Ding Wang ,  Jung Wei Cheng ,  Yu-Min Liang ,  Chien-Hsun Lee ,  Shang-Yun Hou ,  Wei-Yu Chen ,  Collin Jordon Fleshman ,  Kuo-Lung Pan ,  Shu-Rong Chun ,  Sheng-Chi Lin

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H10B80/00 ,  H01L25/18 ,  H01L21/56 ,  H01L23/48

CPC classification number: H01L23/5385 ,  H01L23/3121 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H10B80/00 ,  H01L25/18 ,  H01L21/561 ,  H01L23/481 ,  H01L23/562 ,  H01L2224/16227 ,  H01L24/16 ,  H01L24/29 ,  H01L2224/2929 ,  H01L2924/0665 ,  H01L2224/29386 ,  H01L2924/05442 ,  H01L2924/05432 ,  H01L2924/0503 ,  H01L24/32 ,  H01L2224/32225 ,  H01L24/73 ,  H01L2224/73204 ,  H01L2224/19 ,  H01L2224/211

Abstract: A method includes forming a composite package substrate. The formation of the composite package substrate includes encapsulating an interconnect die in an encapsulant, with the interconnect die including a plurality of through-vias therein, and forming a first plurality of redistribution lines (RDLs) and a second plurality of RDLs on opposite sides of the interconnect die. The method further includes bonding an organic package substrate to the composite package substrate, and bonding a first package component and a second package component to the first plurality of RDLs. The first package component and the second package component are electrically interconnected through the interconnect die and the first plurality of RDLs.

公开(公告)号：US20230253369A1

公开(公告)日：2023-08-10

申请号：US18302496

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Lee ,  Tsung-Ding Wang ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L21/78 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L24/97 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/49827 ,  H01L24/00 ,  H01L21/563 ,  H01L21/78 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L23/3128

Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

公开(公告)号：US11652086B2

公开(公告)日：2023-05-16

申请号：US17087106

申请日：2020-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Hsun Lee ,  Tsung-Ding Wang ,  Mirng-Ji Lii ,  Chen-Hua Yu

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L21/78 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/3675 ,  H01L23/3736 ,  H01L23/49827 ,  H01L24/00 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L23/3128 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/73204 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

公开(公告)号：US11244879B2

公开(公告)日：2022-02-08

申请号：US16746976

申请日：2020-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Yang Yu ,  Chien-Hsun Lee ,  Jung-Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang

IPC: H01L23/31 ,  H01L23/522

Abstract: A semiconductor package including a first semiconductor device, a second semiconductor device, an insulating encapsulant, a redistribution structure and a supporting element is provided. The insulating encapsulant encapsulates the first semiconductor device and the second semiconductor device. The redistribution structure is over the first semiconductor device, the second semiconductor device and the insulating encapsulant. The redistribution structure is electrically connected to the first semiconductor device and the second semiconductor device. The supporting element is embedded in one of the insulating encapsulant and the redistribution structure.

公开(公告)号：US11145639B2

公开(公告)日：2021-10-12

申请号：US16718034

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Wei Cheng ,  Chien-Hsun Lee ,  Chi-Yang Yu ,  Hao-Cheng Hou ,  Hsin-Yu Pan ,  Tsung-Ding Wang

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L21/56 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device.

公开(公告)号：US20210183844A1

公开(公告)日：2021-06-17

申请号：US16718034

申请日：2019-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Wei Cheng ,  Chien-Hsun Lee ,  Chi-Yang Yu ,  Hao-Cheng Hou ,  Hsin-Yu Pan ,  Tsung-Ding Wang

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/498

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first semiconductor device, at least one second semiconductor device, at least one dummy die, an encapsulant and a redistribution structure. The first semiconductor device, the at least one second semiconductor device and at least one dummy die are laterally separated from one another, and laterally encapsulated by the encapsulant. A Young's modulus of the at least one dummy die is greater than a Young's modulus of the encapsulant. A sidewall of the at least one dummy die is substantially coplanar with a sidewall of the encapsulant. The redistribution structure is disposed over the encapsulant, and electrically connected to the first semiconductor device and the at least one second semiconductor device.

公开(公告)号：US10665565B2

公开(公告)日：2020-05-26

申请号：US16221986

申请日：2018-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Jen Lin ,  Tsung-Ding Wang ,  Chien-Hsiun Lee ,  Wen-Hsiung Lu ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L21/768 ,  H01L23/525

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a bump structure disposed on a first substrate and a molding compound in physical contact with the bump structure. The bump structure protrudes from the molding compound. A conductive region is on a second substrate and contacts the bump structure. A no-flow underfill (NUF) material is vertically between the molding compound and the second substrate and laterally surrounds the bump structure. The NUF material is separated from the molding compound.

公开(公告)号：US20240379535A1

公开(公告)日：2024-11-14

申请号：US18779329

申请日：2024-07-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shi Liu ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Hao-Cheng Hou ,  Hung-Jen Lin ,  Jung Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Li-Wei Chou

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.

公开(公告)号：US12142560B2

公开(公告)日：2024-11-12

申请号：US17408840

申请日：2021-08-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Shi Liu ,  Chien-Hsun Lee ,  Jiun Yi Wu ,  Hao-Cheng Hou ,  Hung-Jen Lin ,  Jung Wei Cheng ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Li-Wei Chou

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: An embodiment semiconductor package includes a bare semiconductor chip, a packaged semiconductor chip adjacent the bare semiconductor chip, and a redistribution structure bonded to the bare semiconductor chip and the packaged semiconductor chip. The redistribution structure includes a first redistribution layer having a first thickness; a second redistribution layer having a second thickness; and a third redistribution layer between the first redistribution layer and the second redistribution layer. The third redistribution layer has a third thickness greater than the first thickness and the second thickness. The package further includes an underfill disposed between the bare semiconductor chip and the redistribution structure and a molding compound encapsulating the bare semiconductor chip, the packaged semiconductor chip, and the underfill.