公开(公告)号：US06370667B1

公开(公告)日：2002-04-09

申请号：US09342153

申请日：1999-06-15

Applicant: Takashi Maki

Inventor： Takashi Maki

IPC: H03M1300

CPC classification number: H03M13/6575 ,  H03M13/09

Abstract: The invention relates to a CRC operational calculating method of performing CRC code calculation in order to practice judgment of communication data error, and a CRC operational calculation circuit for performing the operational calculation of the CRC code by use of the hardware. The invention completes the calculation of the cyclic redundancy check with one clock cycle, and performs the calculation with high speed. The CRC calculation circuit is constructed such that the respective bits of a third XNOR output signal are inputted to the input stage of a register as the upper-column four bits including the uppermost-column bit of the CRC code, the respective lower-column three bits including the lowermost-column bit of a second XNOR output signal are inputted to the input stage of the register as the fifth through seventh bits of the CRC code, the respective bits of a fourth XNOR output signal are inputted to the input stage of the register as the eighth through eleventh bits of the CRC code, and the respective bits of a second XOR output signal are inputted to the input stage of the register as the lower-column four bits including the lowermost-column bit of the CRC code.

Abstract translation: 本发明涉及一种执行CRC码计算以执行通信数据错误判定的CRC操作计算方法，以及用于通过硬件执行CRC码的运算计算的CRC运算计算电路。 本发明以一个时钟周期完成循环冗余校验的计算，高速执行计算。 CRC计算电路被构造成使得第三XNOR输出信号的各位被输入到寄存器的输入级，作为包括CRC代码的最上列位的上列四位，相应的下列三位 将包括第二XNOR输出信号的最低列位的位作为CRC码的第五到第七位输入到寄存器的输入级，第四XNOR输出信号的各位被输入到 注册为CRC码的第八到第十一比特，并且第二异或输出信号的各个比特被输入到寄存器的输入级，作为包括CRC码的最低列比特的低列四比特。

公开(公告)号：US5517461A

公开(公告)日：1996-05-14

申请号：US237304

申请日：1994-05-03

Applicant: Kazuyoshi Unno ,  Junichi Shikatani ,  Takashi Maki

Inventor： Kazuyoshi Unno ,  Junichi Shikatani ,  Takashi Maki

IPC: G11C11/413 ,  G11C7/06 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/419 ,  G11C8/00

CPC classification number: G11C11/419 ,  G11C7/067

Abstract: A semiconductor storage device includes a plurality of memory cells, a selecting circuit for selecting, in accordance with address information supplied from an external unit, a memory cell from among the plurality of memory cells, there being a case where a memory cell identified by the address information supplied from the external unit is not present in the plurality of memory cells, a data line to which the plurality of memory cells are coupled, data read out from the selected memory cell being transmitted through the data line, the data line being able to be in a floating state when a memory cell identified by address information is not present in the plurality of memory cells, an amplifier for amplifying the data transmitted through the data line, a latching circuit for latching a potential level of data which has been supplied to the data line, and a control circuit for controlling the latching circuit so that the latching circuit is inactive in a predetermined period including a time at which the data line receives data read out from the memory cell.

Abstract translation: 半导体存储装置包括多个存储单元，选择电路，用于根据从外部单元提供的地址信息，从多个存储单元中选择存储单元，存在由 在多个存储单元中存在从外部单元提供的地址信息，多个存储单元耦合的数据线，从通过数据线发送的所选存储单元读出的数据，数据线能够 当在多个存储单元中不存在由地址信息识别的存储单元时，处于浮置状态，放大器，用于放大通过数据线发送的数据;锁存电路，用于锁存已经提供的数据的潜在电平 以及用于控制锁存电路的控制电路，使得锁存电路在包括a的预定周​​期内不起作用 数据线接收从存储单元读出的数据的时间。