公开(公告)号：US5517461A

公开(公告)日：1996-05-14

申请号：US237304

申请日：1994-05-03

申请人： Kazuyoshi Unno ,  Junichi Shikatani ,  Takashi Maki

发明人： Kazuyoshi Unno ,  Junichi Shikatani ,  Takashi Maki

IPC分类号： G11C11/413 ,  G11C7/06 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409 ,  G11C11/419 ,  G11C8/00

CPC分类号： G11C11/419 ,  G11C7/067

摘要： A semiconductor storage device includes a plurality of memory cells, a selecting circuit for selecting, in accordance with address information supplied from an external unit, a memory cell from among the plurality of memory cells, there being a case where a memory cell identified by the address information supplied from the external unit is not present in the plurality of memory cells, a data line to which the plurality of memory cells are coupled, data read out from the selected memory cell being transmitted through the data line, the data line being able to be in a floating state when a memory cell identified by address information is not present in the plurality of memory cells, an amplifier for amplifying the data transmitted through the data line, a latching circuit for latching a potential level of data which has been supplied to the data line, and a control circuit for controlling the latching circuit so that the latching circuit is inactive in a predetermined period including a time at which the data line receives data read out from the memory cell.

摘要翻译： 半导体存储装置包括多个存储单元，选择电路，用于根据从外部单元提供的地址信息，从多个存储单元中选择存储单元，存在由 在多个存储单元中存在从外部单元提供的地址信息，多个存储单元耦合的数据线，从通过数据线发送的所选存储单元读出的数据，数据线能够 当在多个存储单元中不存在由地址信息识别的存储单元时，处于浮置状态，放大器，用于放大通过数据线发送的数据;锁存电路，用于锁存已经提供的数据的潜在电平 以及用于控制锁存电路的控制电路，使得锁存电路在包括a的预定周​​期内不起作用 数据线接收从存储单元读出的数据的时间。

公开(公告)号：US5436485A

公开(公告)日：1995-07-25

申请号：US365173

申请日：1994-12-28

申请人： Junichi Shikatani ,  Tetsu Tanizawa ,  Mitsugu Naito

发明人： Junichi Shikatani ,  Tetsu Tanizawa ,  Mitsugu Naito

IPC分类号： H01L27/118 ,  H01L27/02 ,  H01L27/10

CPC分类号： H01L27/11807 ,  Y10S257/909

摘要： A master-slice type semiconductor integrated circuit device includes a first transistor, and a second transistor. The first and second transistors are arranged side by side in a first direction. The first and second transistors respectively have first and second gate electrodes extending in a second direction perpendicular to the first direction. The first gate electrode has a first portion in which two gate contacts arranged in the first direction can be made. The second gate electrode has a second portion in which two gate contacts arranged in the first direction can be made.

摘要翻译： 主切片式半导体集成电路器件包括第一晶体管和第二晶体管。 第一和第二晶体管沿第一方向并排布置。 第一和第二晶体管分别具有在垂直于第一方向的第二方向上延伸的第一和第二栅电极。 第一栅电极具有第一部分，其中可以制造沿第一方向布置的两个栅极触点。 第二栅电极具有第二部分，其中可以制造沿第一方向布置的两个栅极触点。

公开(公告)号：US5040150A

公开(公告)日：1991-08-13

申请号：US527977

申请日：1990-05-24

申请人： Mitsugu Naitoh ,  Junichi Shikatani

发明人： Mitsugu Naitoh ,  Junichi Shikatani

IPC分类号： G01R31/3185 ,  G11C29/12

CPC分类号： G11C29/12 ,  G01R31/318505 ,  G11C11/16

摘要： A semiconductor integrated circuit device comprising a first circuit forming a random logic and outputting a plurality of first parallel data of plural bits, a second circuit which receives the plurality of first parallel data and supplies a plurality of second parallel data of plural bits to the first circuit, and a test circuit which divides a part of external parallel data of plural bits smaller in number than the first parallel data into a plurality of third parallel data of plural bits in such a manner that the plurality of third parallel data correspond in number to the plurality of first parallel data.

公开(公告)号：US5253207A

公开(公告)日：1993-10-12

申请号：US793968

申请日：1991-11-18

申请人： Junichi Shikatani

发明人： Junichi Shikatani

IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C7/00

CPC分类号： G11C8/16

摘要： A semiconductor memory device in which dual ports are provided for selecting a specific memory cell from a memory cell matrix includes a driving state detection unit for detecting the state of driving word lines of the two ports and delivering a detection signal based on the detection, where one of the ports is in the writing state with regard to the memory cell, and a bit line short-circuiting unit responsive to the detection signal from the driving state detection unit for realizing a short-circuit between predetermined bit lines.

公开(公告)号：US5369646A

公开(公告)日：1994-11-29

申请号：US978067

申请日：1992-11-18

申请人： Junichi Shikatani

发明人： Junichi Shikatani

IPC分类号： G01R31/317 ,  G01R31/28 ,  G01R31/3185 ,  G11C7/10 ,  G11C29/00 ,  G11C29/12 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H03K19/177 ,  H04B17/00

CPC分类号： H03K19/17772 ,  G01R31/318516 ,  G11C7/1006 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17764 ,  H03K19/1778

摘要： A semiconductor integrated circuit device includes a logic cell array having a plurality of logic cells arranged in a matrix having a plurality of rows and columns. The logic cells respectively have input terminals and output terminals. Also, the device includes interconnection lines mutually connecting the logic cells via the input and output terminals of the logic cells so that desired logic circuits are formed, and a plurality of switches which are respectively provided for the logic cells and selectively connect the output terminals of the logic cells to the interconnection lines. Further, the device includes a test circuit for directly supplying the input terminals of the logic cells with desired data used for testing the semiconductor integrated circuit device in a state where a plurality of switches selectively disconnect the output terminals of the logic cells from the interconnection lines. The output line of a cell is disconnected from the interconnection line to the input of the following cell. The interconnection line is then connected to an input/output line which is switched to an input state and the desired test signal is supplied to the input of the following cell. The state of the following cell can then be evaluated to delete errors in the cell performance.

摘要翻译： 半导体集成电路器件包括具有以具有多个行和列的矩阵排列的多个逻辑单元的逻辑单元阵列。 逻辑单元分别具有输入端子和输出端子。 此外，该装置还包括互连线，逻辑单元经由逻辑单元的输入和输出端相互连接以形成期望的逻辑电路，并且分别为逻辑单元提供并选择性地连接逻辑单元的输出端的多个开关 逻辑单元到互连线。 此外，该装置包括用于在多个开关选择性地将逻辑单元的输出端与互连线断开的状态下直接向逻辑单元的输入端提供用于测试半导体集成电路器件的期望数据的测试电路 。 单元的输出线从互连线断开到以下单元的输入。 然后将互连线连接到输入/输出线，该输入/输出线被切换到输入状态，并且将期望的测试信号提供给下一个单元的输入。 然后可以评估以下单元格的状态以删除单元格性能中的错误。

公开(公告)号：US5345425A

公开(公告)日：1994-09-06

申请号：US852638

申请日：1992-08-06

申请人： Junichi Shikatani

发明人： Junichi Shikatani

IPC分类号： G11C11/41 ,  G11C8/16 ,  G11C11/417 ,  H01L27/10 ,  G11C11/40

CPC分类号： G11C8/16

摘要： A semiconductor memory device has a memory part, first and second write bit lines coupled to the memory part and used exclusively for writing information into the memory part and first and second read bit lines coupled to the memory part and used exclusively for reading information, held in the memory part, from the memory part. A short-circuiting circuit short-circuits the first and second read bit lines and thereby sets them to the same potential, in a write mode of operation of the semiconductor memory device in which information is written into the memory part via the first and second write bit lines. The short-circuiting circuit permits a read operation to be performed immediately following a write operation, at a high speed.

摘要翻译： PCT No.PCT / JP91 / 01578 Sec。 371日期：1992年8月6日 102（e）日期1992年8月6日PCT 1991年11月19日PCT公布。 出版物WO92 / 09085 日期：1992年5月29日。半导体存储器件具有存储器部分，第一和第二写入位线耦合到存储器部分，并专门用于将信息写入存储器部分，以及耦合到存储器部分的第一和第二读取位线并使用 专用于从存储器部分保存在存储器部分中的信息。 短路电路使第一和第二读取位线短路，从而将半导体存储器件的写入操作模式设置为相同的电位，其中通过第一和第二写入将信息写入存储器部分 位线。 短路电路允许在写入操作之后立即以高速执行读取操作。

公开(公告)号：US5341383A

公开(公告)日：1994-08-23

申请号：US736999

申请日：1991-07-29

申请人： Junichi Shikatani ,  Shigeki Kawahara

发明人： Junichi Shikatani ,  Shigeki Kawahara

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318516

摘要： A circuit arrangement formed on an IC chip includes a first type block and a second type block. The first type block has a plurality of cells arranged into rows and columns and a plurality of transistors respectively provided for the cells. Each of the transistors has a first terminal coupled to a corresponding one of the cells, a second terminal and a gate terminal. The second type block is a block which is not required to be test in a way identical to that for the first type block. A probe line driver tests the cells in the first type block, and is located along a first edge of the first type block. A plurality of probe lines extend from the probe line driver and run in the first type block. Each of the probe lines is connected to the gate of a corresponding one of the transistors. A sense circuit senses data read out from the cells via a plurality of sense lines running in the first type block. Each of the sense lines is connected to the second terminal of a corresponding one of the transistors. The sense circuit is located along a second edge of the first type block substantially perpendicular to the first edge of the first type block. A test control circuit controls the probe line driver and the sense circuit so that data are successively read out from the cells and transferred to the sense lines via the transistors. The test control circuit is adjacent to the probe line driver and the sense circuit.

摘要翻译： 形成在IC芯片上的电路装置包括第一类型块和第二类型块。 第一类型块具有排列成行和列的多个单元和分别为单元提供的多个晶体管。 每个晶体管具有耦合到相应的一个单元的第一端子，第二端子和栅极端子。 第二类型块是不需要以与第一类型块相同的方式测试的块。 探针线驱动器测试第一类型块中的单元，并且沿着第一类型块的第一边缘定位。 多个探针线从探针线驱动器延伸并在第一类型块中运行。 每个探针线连接到相应的一个晶体管的栅极。 感测电路通过在第一类型块中运行的多条感测线路感测从单元读出的数据。 每个感测线连接到相应的一个晶体管的第二端子。 感测电路沿着基本上垂直于第一类型块的第一边缘的第一类型块的第二边缘定位。 测试控制电路控制探针线驱动器和感测电路，使得数据从单元连续地读出并通过晶体管传送到感测线。 测试控制电路与探测线驱动器和感测电路相邻。

公开(公告)号：US5060200A

公开(公告)日：1991-10-22

申请号：US347320

申请日：1989-05-04

申请人： Daisuke Miura ,  Junichi Shikatani

发明人： Daisuke Miura ,  Junichi Shikatani

IPC分类号： G11C8/14 ,  G11C8/16 ,  G11C11/41

CPC分类号： G11C8/16 ,  G11C11/41 ,  G11C8/14

摘要： A partial random access memory includes a plurality of memory cells arrayed in matrix form, a plurality of pairs of bit lines extending in a column direction, each of the plurality of memory cells being coupled to corresponding one of pairs of bit lines, and a plurality of word lines including a plurality of first and second word lines. One first word line and one second word line are paired and arranged on both sides of an arrangement of the memory cells in a row direction. Each of the plurality of memory cells is connected to at least one of the first and second word lines. An activating circuit coupled to the plurality of word lines separately activates the first and second word lines, depending on an address signal supplied from an external circuit, thereby independently selecting the first and second word lines. An input/output circuit coupled to the plurality of bit lines writes input data into corresponding memory cells and reads out output data from corresponding memory cells.