公开(公告)号：US20050259464A1

公开(公告)日：2005-11-24

申请号：US11189851

申请日：2005-07-27

申请人： Takeshi Kajiyama ,  Tomomasa Ueda ,  Tatsuya Kishi ,  Hisanori Aikawa ,  Masatoshi Yoshikawa ,  Yoshiaki Asao ,  Hiroaki Yoda

发明人： Takeshi Kajiyama ,  Tomomasa Ueda ,  Tatsuya Kishi ,  Hisanori Aikawa ,  Masatoshi Yoshikawa ,  Yoshiaki Asao ,  Hiroaki Yoda

IPC分类号： H01L27/105 ,  G11B5/33 ,  G11C11/14 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

CPC分类号： G11C11/16 ,  B82Y10/00 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12

摘要： A magnetic random access memory concerning an example of the present invention comprises a magneto resistive element, a first insulating layer which covers side surfaces of the magneto resistive element, a second insulating layer which is arranged on the first insulating layer and has a first groove on the magneto resistive element, a write line which fills the first groove and is connected with the magneto resistive element, and a third insulating layer which is arranged between the first and second insulating layers except a bottom portion of the first groove and has an etching selection ratio with respect to at least the first and second insulating layers.

摘要翻译： 关于本发明的实例的磁性随机存取存储器包括磁阻元件，覆盖磁阻元件的侧表面的第一绝缘层，布置在第一绝缘层上并具有第一凹槽的第二绝缘层 磁阻元件，填充第一沟槽并与磁阻元件连接的写入线以及布置在除了第一沟槽的底部之外的第一和第二绝缘层之间的第三绝缘层，并且具有蚀刻选择 至少相对于第一绝缘层和第二绝缘层。

公开(公告)号：US06967864B2

公开(公告)日：2005-11-22

申请号：US10866129

申请日：2004-06-14

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L27/105 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  G11C7/00

CPC分类号： H01L27/222 ,  B82Y10/00

摘要： A semiconductor memory device includes a semiconductor substrate, and a first magneto resistive element separated from the semiconductor substrate, and including a first magnetic layer and a first nonmagnetic layer. The first magnetic layer and the first nonmagnetic layer are formed in a direction perpendicular to the semiconductor substrate.

摘要翻译： 半导体存储器件包括半导体衬底和与半导体衬底分离的第一磁阻元件，并且包括第一磁性层和第一非磁性层。 第一磁性层和第一非磁性层在垂直于半导体衬底的方向上形成。

公开(公告)号：US20050141148A1

公开(公告)日：2005-06-30

申请号：US11000093

申请日：2004-12-01

申请人： Hisanori Aikawa ,  Tomomasa Ueda ,  Tatsuya Kishi ,  Takeshi Kajiyama ,  Yoshiaki Asao ,  Hiroaki Yoda

发明人： Hisanori Aikawa ,  Tomomasa Ueda ,  Tatsuya Kishi ,  Takeshi Kajiyama ,  Yoshiaki Asao ,  Hiroaki Yoda

IPC分类号： G11B5/33 ,  G11B5/39

CPC分类号： G11B5/39

摘要： It is possible to reduce writing current without causing fluctuation of the writing characteristic. A magnetic memory includes: a magnetoresistance effect element having a magnetization pinned layer whose magnetization direction is pinned, a storage layer whose magnetization direction is changeable, and a non-magnetic layer provided between the magnetization pinned layer and the storage layer; and a first wiring layer which is electrically connected to the magnetoresistance effect element and extends in a direction substantially perpendicular to a direction of an easy magnetization axis of the storage layer, an end face of the magnetoresistance effect element substantially perpendicular to the direction of the easy magnetization axis of the storage layer and an end face of the first wiring layer substantially perpendicular to the direction of the easy magnetization axis being positioned on the same plane.

摘要翻译： 可以减小写入电流而不引起写入特性的波动。 磁存储器包括：磁阻效应元件，具有其磁化方向被钉扎的磁化钉扎层，其磁化方向可变的存储层和设置在磁化钉扎层与存储层之间的非磁性层; 以及第一布线层，其电连接到所述磁阻效应元件并且沿着与所述存储层的容易磁化轴方向大致垂直的方向延伸，所述磁阻效应元件的端面基本上垂直于所述容易的方向 存储层的磁化轴和基本上垂直于易磁化轴的方向的第一布线层的端面位于同一平面上。

公开(公告)号：US06822896B2

公开(公告)日：2004-11-23

申请号：US10847624

申请日：2004-05-18

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： G11C1100

CPC分类号： G11C11/15

摘要： MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. Upper lines and lower lines extending in the X direction are connected to the MTJ elements. The number of MTJ elements arranged in each portion is gradually increased from a lower portion towards an upper portion. With respect to the upper lines, the upper lines arranged in the lower portion are connected to transistors present near an array of the MTJ elements, and the upper lines arranged in the upper portion are connected to transistors distant from the array of the MTJ elements. Also with respect to the lower lines, the lower lines in the lower portion are connected to transistors nearer to the array of the TRM elements than the lower lines in the upper portion.

公开(公告)号：US06807086B2

公开(公告)日：2004-10-19

申请号：US10305988

申请日：2002-11-29

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： G11C1100

CPC分类号： G11C11/15 ,  G11C11/1659 ,  G11C2213/71

摘要： MTJ elements are accumulated in a plurality of portions on a semiconductor substrate. A first conductive line functioning as a read line and extending in the X direction is connected to pin layers of the MTJ elements. A second conductive line functioning as a write line and read line and extending in the X direction is connected to free layers of the MTJ elements. A write line extends in the Y direction and is shared with two MTJ elements present above and below the write line. The two MTJ elements present above and below the write line are arranged symmetric to the write line.

摘要翻译： MTJ元件被累积在半导体衬底上的多个部分中。 用作读取线并沿X方向延伸的第一导电线连接到MTJ元件的引脚层。 用作写入线和读取线并沿X方向延伸的第二导线连接到MTJ元件的自由层。 写行在Y方向上延伸，并与写入行上方和下方的两个MTJ元素共享。 写入线上方和下方的两个MTJ元件与写入线对称。

公开(公告)号：US06632723B2

公开(公告)日：2003-10-14

申请号：US10132520

申请日：2002-04-26

申请人： Shinichi Watanabe ,  Takashi Ohsawa ,  Kazumasa Sunouchi ,  Yoichi Takegawa ,  Takeshi Kajiyama

发明人： Shinichi Watanabe ,  Takashi Ohsawa ,  Kazumasa Sunouchi ,  Yoichi Takegawa ,  Takeshi Kajiyama

IPC分类号： H01L2176

CPC分类号： H01L21/823481 ,  H01L21/763

摘要： A semiconductor device is disclosed, which includes a semiconductor substrate, drain and source regions of a MOS transistor, a gate electrode formed on a surface of a channel region of the MOS transistor trench type element isolation regions in each of which an insulating film is formed on a surface of a trench formed in the surface of the semiconductor substrate, the element isolation regions sandwiching the channel region from opposite sides thereof in a channel width direction, and a conductive material layer for a back gate electrode, which is embedded in a trench of at least one of the element isolation regions, configured to be supplied with a predetermined voltage to make an depletion layer in a region of the semiconductor substrate under the channel region of the MOS transistor or to voltage-control the semiconductor substrate region.

摘要翻译： 公开了一种半导体器件，其包括半导体衬底，MOS晶体管的漏极和源极区域，形成在MOS晶体管沟槽型元件隔离区域的沟道区域的表面中的栅电极，其中形成绝缘膜 在形成在半导体衬底的表面中的沟槽的表面上，元件隔离区域在沟道宽度方向上从其相对侧夹着沟道区域，以及嵌入在沟槽宽度方向上的背栅电极用导电材料层 被配置为被提供预定电压以在半导体衬底的位于MOS晶体管的沟道区域的区域内的耗尽层或者对半导体衬底区域进行电压控制的元件隔离区域中的至少一个。 PTEXT>

公开(公告)号：US08492830B2

公开(公告)日：2013-07-23

申请号：US13236534

申请日：2011-09-19

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L29/66 ,  H01L21/336

CPC分类号： H01L21/76224 ,  H01L29/785

摘要： According to one embodiment, a semiconductor memory device includes a semiconductor substrate having a gate groove and first to third grooves, the first to third grooves being formed on a bottom surface of the gate groove and the third groove being formed between the first and second grooves, and a gate electrode having a first gate portion formed in the first groove, a second gate portion formed in the second groove, a third gate portion formed in the third groove, and a fourth gate portion formed in the gate groove. A cell transistor having the gate electrode has a first channel region formed in the semiconductor substrate between the first and third gate portions and a second channel region formed in the semiconductor substrate between the second and third gate portions.

摘要翻译： 根据一个实施例，半导体存储器件包括具有栅极沟槽和第一至第三沟槽的半导体衬底，第一至第三沟槽形成在栅极沟槽的底表面上，第三沟槽形成在第一和第二沟槽之间 以及栅电极，其具有形成在第一槽中的第一栅极部分，形成在第二槽中的第二栅极部分，形成在第三槽中的第三栅极部分和形成在栅极沟槽中的第四栅极部分。 具有栅电极的单元晶体管具有形成在第一和第三栅极部分之间的半导体衬底中的第一沟道区域和形成在第二栅极部分和第三栅极部分之间的半导体衬底中的第二沟道区域。

公开(公告)号：US20110283299A1

公开(公告)日：2011-11-17

申请号：US13106385

申请日：2011-05-12

申请人： Yoshimichi Takano ,  Nobuaki Onagi ,  Kohji Tsukahara ,  Haruki Tokumaru ,  Daiichi Koide ,  Takeshi Kajiyama ,  Masami Nishida

发明人： Yoshimichi Takano ,  Nobuaki Onagi ,  Kohji Tsukahara ,  Haruki Tokumaru ,  Daiichi Koide ,  Takeshi Kajiyama ,  Masami Nishida

IPC分类号： G11B17/04 ,  G11B23/03

CPC分类号： G11B17/225 ,  G11B23/0021 ,  G11B23/0035 ,  G11B23/005

摘要： A disk laminate includes thin disks laminated to each other, which are to be suctioned and conveyed; and spacers provided between the thin disks to prevent the thin disks from directly contacting each other, the spacers having air permeability.

摘要翻译： 圆盘叠片包括彼此层叠的薄盘，它们被抽吸和输送; 以及设置在所述薄盘之间的间隔件，以防止所述薄盘彼此直接接触，所述间隔件具有透气性。

公开(公告)号：US08022439B2

公开(公告)日：2011-09-20

申请号：US12636633

申请日：2009-12-11

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L31/0336 ,  H01L31/109 ,  H01L21/8234 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78696

摘要： Two first semiconductor layers are on a silicon substrate at a given distance from each other. Two second semiconductor layers are on the respective first semiconductor layers and includes a material different from a material of the first semiconductor layers. A first channel region is formed like a wire between the two second semiconductor layers. A first insulating layer is around the first channel region. A second insulating film is on each of opposite side surfaces of the two first semiconductor layers. A third insulating film is on each of opposite side surfaces of the two second semiconductor layers. A gate electrode is on the first, second, and third insulating films. Film thickness of the second insulating film is larger than film thickness of the first insulating film.

摘要翻译： 两个第一半导体层位于硅衬底上彼此以给定的距离。 两个第二半导体层位于相应的第一半导体层上，并且包括与第一半导体层的材料不同的材料。 第一沟道区域在两个第二半导体层之间形成为线状。 第一绝缘层围绕第一沟道区域。 第二绝缘膜位于两个第一半导体层的相对侧表面的每一个上。 第三绝缘膜位于两个第二半导体层的相对侧表面的每一个上。 栅极位于第一，第二和第三绝缘膜上。 第二绝缘膜的膜厚比第一绝缘膜的膜厚大。

公开(公告)号：US20110072446A1

公开(公告)日：2011-03-24

申请号：US12882949

申请日：2010-09-15

申请人： Nobuaki Onagi ,  Yasutomo Aman ,  Haruki Tokumaru ,  Yoshimichi Takano ,  Daiichi Koide ,  Takeshi Kajiyama ,  Masami Nishida

发明人： Nobuaki Onagi ,  Yasutomo Aman ,  Haruki Tokumaru ,  Yoshimichi Takano ,  Daiichi Koide ,  Takeshi Kajiyama ,  Masami Nishida

IPC分类号： G11B17/028

CPC分类号： G11B17/0284 ,  G11B17/056 ,  G11B17/32

摘要： A disclosed disk clamping mechanism includes a turntable fixed on a rotational shaft of a spindle motor to rotate a flexible thin optical disk, a stabilizer member configured to suppress a run-out of the flexible thin optical disk by an applying aerodynamic force to the rotating flexible thin optical disk so as to stabilize the run-out of the rotating flexible thin optical disk, and a clamper movably supported in a center of the stabilizer member in a direction perpendicular to a surface of the flexible thin optical disk. In the disclosed disk clamping mechanism, the flexible thin optical disk is sandwiched between the turntable and the clamper such that the turntable and the clamper rotate the flexible thin optical member sandwiched in-between.

摘要翻译： 所公开的盘夹紧机构包括：固定在主轴电动机的旋转轴上以旋转柔性薄型光盘的转盘;稳定器构件，其被配置为通过施加空气动力力来抑制柔性薄型光盘的旋转， 以便稳定旋转的柔性薄型光盘的跳动，以及在垂直于柔性薄型光盘的表面的方向上可移动地支撑在稳定器构件的中心的夹持器。 在所公开的光盘夹紧机构中，柔性薄型光盘被夹在转台和夹持器之间，使得转盘和夹持器旋转夹在其间的柔性薄光学部件。