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公开(公告)号：US11785867B2
公开(公告)日：2023-10-10
申请号：US17372528
申请日：2021-07-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chung-Yi Chiu
CPC classification number: H10N70/826 , H10B63/00 , H10N70/011 , H10N70/231
Abstract: A memory device includes a substrate, a memory unit, and a first spacer layer. The memory unit is disposed on the substrate, and the memory unit includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction, and the memory material layer is disposed between the first electrode and the second electrode in the vertical direction. The first spacer layer is disposed on a sidewall of the memory unit. The first spacer layer includes a first portion and a second portion. The first portion is disposed on a sidewall of the first electrode, the second portion is disposed on a sidewall of the second electrode, and a thickness of the second portion in a horizontal direction is greater than a thickness of the first portion in the horizontal direction.
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公开(公告)号：US20230210013A1
公开(公告)日：2023-06-29
申请号：US18116305
申请日：2023-03-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo
Abstract: A semiconductor device includes a substrate having a logic region and a memory region, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer disposed on and directly contacting a top surface of the first interlayer dielectric layer. A portion of the top surface of the first interlayer dielectric layer on the memory region is lower than another portion of the top surface of the first interlayer dielectric layer on the logic region. A memory stack structure is disposed in the first interlayer dielectric layer on the memory region. A passivation layer covers a top surface and sidewalls of the memory stack structure and is in direct contact with the second interlayer dielectric layer. An upper contact structure penetrates through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure and directly contacts the memory stack structure.
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公开(公告)号：US20220399492A1
公开(公告)日：2022-12-15
申请号：US17372528
申请日：2021-07-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chung-Yi Chiu
Abstract: A memory device includes a substrate, a memory unit, and a first spacer layer. The memory unit is disposed on the substrate, and the memory unit includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction, and the memory material layer is disposed between the first electrode and the second electrode in the vertical direction. The first spacer layer is disposed on a sidewall of the memory unit. The first spacer layer includes a first portion and a second portion. The first portion is disposed on a sidewall of the first electrode, the second portion is disposed on a sidewall of the second electrode, and a thickness of the second portion in a horizontal direction is greater than a thickness of the first portion in the horizontal direction.
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公开(公告)号：US20220376166A1
公开(公告)日：2022-11-24
申请号：US17341316
申请日：2021-06-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chia-Chang Hsu
Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection.
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公开(公告)号：US20210028352A1
公开(公告)日：2021-01-28
申请号：US17064614
申请日：2020-10-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Meng-Jun Wang , Yi-Wei Tseng , Yu-Tsung Lai , Jiunn-Hsiung Liao
Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming an etch stop layer on the first IMD layer; forming a second IMD layer on the etch stop layer; forming a patterned hard mask on the second IMD layer; performing a first etching process to form a contact hole in the second IMD layer for exposing the etch stop layer; performing a second etching process to remove the patterned hard mask; performing a third etching process to remove the etch stop layer and the first IMD layer for exposing the MTJ; and forming a metal interconnection in the contact hole.
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Patent Agency Ranking
公开(公告)号：US20210020693A1
公开(公告)日：2021-01-21
申请号：US16544923
申请日：2019-08-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Tai-Cheng Hou , Yu-Tsung Lai , Jiunn-Hsiung Liao
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.
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公开(公告)号：US20190096748A1
公开(公告)日：2019-03-28
申请号：US15712153
申请日：2017-09-22
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Yu-Tsung Lai , Jiunn-Hsiung Liao
IPC: H01L21/768
Abstract: A method for fabricating a semiconductor device includes the steps of: providing a first dielectric layer having a metal layer therein; forming a second dielectric layer on the first dielectric layer and the metal layer; forming a metal oxide layer on the second dielectric layer; performing a first etching process by using a chlorine-based etchant to remove part of the metal oxide layer to forma via opening and expose the second dielectric layer; forming a block layer on sidewalls of the metal oxide layer and a top surface of the second dielectric layer; and performing a second etching process by using a fluorine-based etchant to remove part of the block layer and part of the second dielectric layer for exposing a top surface of the metal layer.
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公开(公告)号：US20240422989A1
公开(公告)日：2024-12-19
申请号：US18223043
申请日：2023-07-18
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chung-Yi Chiu
Abstract: A resistive memory device includes a dielectric layer, a trench, a first resistive switching element, a diode via structure, and a signal line structure. The trench is disposed in the dielectric layer. The first resistive switching element is disposed in the trench. The first resistive switching element includes a first bottom electrode, a first top electrode disposed above the first bottom electrode, and a first variable resistance layer disposed between the first bottom electrode and the first top electrode. The diode via structure is disposed in the dielectric layer and located under the trench, and the diode via structure is connected with the first bottom electrode. The signal line structure is disposed in the trench, a part of the signal line structure is disposed on the first resistive switching element, and the signal line structure is electrically connected with the first top electrode.
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公开(公告)号：US12029138B2
公开(公告)日：2024-07-02
申请号：US18201741
申请日：2023-05-24
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chia-Chang Hsu
CPC classification number: H10N50/80 , H01L27/0248 , H10B61/22
Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.
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公开(公告)号：US12022739B2
公开(公告)日：2024-06-25
申请号：US18116277
申请日：2023-03-01
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo
Abstract: A method for forming a semiconductor device includes the steps of providing a substrate having a memory region and a logic region, forming a memory stack structure on the memory region, forming a passivation layer covering a top surface and sidewalls of the memory stack structure, forming a first interlayer dielectric layer on the passivation layer, performing a post-polishing etching back process to remove a portion of the first interlayer dielectric layer and a portion of the passivation layer on the top surface of the memory stack structure, forming a second interlayer dielectric layer on the first interlayer dielectric layer and directly contacting the passivation layer, and forming an upper contact structure through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure to contact the memory stack structure.
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