公开(公告)号：US20210288107A1

公开(公告)日：2021-09-16

申请号：US17336279

申请日：2021-06-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Tai-Cheng Hou ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

Abstract: A semiconductor device includes a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, a first top electrode on the first MTJ and a second top electrode on the second MTJ, a passivation layer between the first MTJ and the second MTJ, and an ultra low-k (ULK) dielectric layer on and directly contacting the passivation layer and around the first MTJ and the second MTJ. Preferably, a top surface of the passivation layer includes a V-shape and a valley point of the V-shape is higher than a bottom surface of the first top electrode.

公开(公告)号：US11056536B2

公开(公告)日：2021-07-06

申请号：US16544923

申请日：2019-08-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Tai-Cheng Hou ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.

公开(公告)号：US10847709B1

公开(公告)日：2020-11-24

申请号：US16439712

申请日：2019-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Meng-Jun Wang ,  Yi-Wei Tseng ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A semiconductor device includes: a magnetic tunneling junction (MTJ) on a substrate; a first inter-metal dielectric (IMD) layer around the MTJ; a metal interconnection on and directly contacting the MTJ; a second IMD layer on the first IMD layer and around the metal interconnection; and a metal oxide layer on the second IMD layer and around the metal interconnection.

公开(公告)号：US12290004B2

公开(公告)日：2025-04-29

申请号：US18674889

申请日：2024-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H01L27/02 ,  H10B61/00

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

公开(公告)号：US12274175B2

公开(公告)日：2025-04-08

申请号：US17565496

申请日：2021-12-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo

IPC: G11C11/00 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a first inter-metal dielectric (IMD) layer on a substrate, a first metal interconnection in the first IMD layer, a second IMD layer on the first IMD layer, a second metal interconnection in the second IMD layer, a bottom electrode on the second metal interconnection, a magnetic tunneling junction (MTJ) on the bottom electrode, a top electrode on the MTJ, a cap layer adjacent to the MTJ, a third IMD layer on the MTJ, and a third metal interconnection in the third IMD layer for connecting the top electrode and the first metal interconnection. Preferably, a width of a bottom surface of the MTJ is less than a width of a top surface of the MTJ.

公开(公告)号：US12213389B2

公开(公告)日：2025-01-28

申请号：US18239104

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10N70/00 ,  H10B63/10 ,  H10N70/20

Abstract: A memory device includes a substrate, a memory unit disposed on the substrate, a first spacer layer, and a second spacer layer. The memory unit includes a first electrode, a second electrode disposed above the first electrode, and a memory material layer disposed between the first electrode and the second electrode. The first spacer layer is disposed on a sidewall of the memory unit and includes a first portion disposed on a sidewall of the first electrode, a second portion disposed on a sidewall of the second electrode, and a bottom portion. A thickness of the second portion is greater than that of the first portion. The second spacer layer is disposed on the first spacer layer. A material composition of the second spacer layer is different from that of the first spacer layer. The bottom portion is disposed between the substrate and the second spacer layer.

公开(公告)号：US12193342B2

公开(公告)日：2025-01-07

申请号：US18239108

申请日：2023-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chung-Yi Chiu

IPC: H10N70/00 ,  H10B63/10 ,  H10N70/20

Abstract: A manufacturing method of a memory device includes following steps. A memory unit including a first electrode, a second electrode, and a memory material layer is formed on a substrate. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A first spacer layer including a first portion, a second portion, and a third portion is formed on a sidewall of the memory unit. The first portion is disposed on a sidewall of the first electrode. The second portion is disposed on a sidewall of the second electrode. The third portion is disposed above the memory unit in the vertical direction and connected with the second portion. A thickness of the second portion in a horizontal direction is greater than that of the first portion in the horizontal direction.

公开(公告)号：US20240315146A1

公开(公告)日：2024-09-19

申请号：US18674889

申请日：2024-05-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H01L27/02 ,  H10B61/00

CPC classification number: H10N50/80 ,  H01L27/0248 ,  H10B61/22

Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.

公开(公告)号：US12096697B2

公开(公告)日：2024-09-17

申请号：US18381627

申请日：2023-10-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo ,  Chia-Chang Hsu

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01

CPC classification number: H10N50/80 ,  H10B61/00 ,  H10N50/01

Abstract: A semiconductor device includes a substrate, a first MTJ structure, a second MTJ structure, an interconnection structure including a first metal interconnection and a second metal interconnection disposed on and contacting the first metal interconnection, a fifth metal interconnection, and a sixth metal interconnection. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction. The fifth metal interconnection and the sixth metal interconnection are disposed under and contact the first MTJ structure and the second MTJ structure, respectively. The fifth metal interconnection includes a barrier layer and a metal layer disposed on the barrier layer. A length of the first MTJ structure in the first horizontal direction is greater than a length of the metal layer in the first horizontal direction.

公开(公告)号：US12010923B2

公开(公告)日：2024-06-11

申请号：US18116305

申请日：2023-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Kuo

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A semiconductor device includes a substrate having a logic region and a memory region, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer disposed on and directly contacting a top surface of the first interlayer dielectric layer. A portion of the top surface of the first interlayer dielectric layer on the memory region is lower than another portion of the top surface of the first interlayer dielectric layer on the logic region. A memory stack structure is disposed in the first interlayer dielectric layer on the memory region. A passivation layer covers a top surface and sidewalls of the memory stack structure and is in direct contact with the second interlayer dielectric layer. An upper contact structure penetrates through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure and directly contacts the memory stack structure.