公开(公告)号：US09859335B1

公开(公告)日：2018-01-02

申请号：US15367690

申请日：2016-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Liang Yi ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L29/00 ,  H01L27/24 ,  H01L29/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1683

Abstract: A semiconductor device includes an interconnection formed above a substrate, and the interconnection comprising interconnect layers respectively buried in dielectric layers; a lower conducting layer formed above the substrate; a memory cell structure formed on the lower conducting layer and buried in one of the dielectric layers; an upper conducting layer formed on the memory cell structure. The memory cell structure includes a bottom electrode formed on and electrically connected to the lower conducting layer; a transitional metal oxide (TMO) layer formed on the bottom electrode; and a top electrode formed on the TMO layer, wherein the upper conducting layer is formed on the top electrode and electrically connected to the top electrode. Also, the lower conducting layer and the upper conducting layer are positioned in the different dielectric layers.

公开(公告)号：US09806255B1

公开(公告)日：2017-10-31

申请号：US15455142

申请日：2017-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Liang Yi ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1691

Abstract: A resistive random access memory includes a lower electrode, an upper electrode and a resistive layer between the lower electrode and the upper electrode, wherein the resistive layer includes a constant-resistance portion and a variable-resistance portion surrounding the constant-resistance portion.