公开(公告)号：US20190229265A1

公开(公告)日：2019-07-25

申请号：US16372642

申请日：2019-04-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsia-Wei Chen ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Chih-Yang Chang ,  Chin-Chieh Yang ,  Yu-Wen Liao ,  Wen-Chun You ,  Sheng-Hung Shih

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/122 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1666 ,  H01L45/1683

Abstract: Some embodiments relate to a device. The device includes a top electrode and a via disposed over the top electrode. A peripheral upper surface of the top electrode is above a central upper surface of the top electrode, and a tapered inner sidewall of the top electrode connects the peripheral upper surface to the central upper surface. The via establishes electrical contact with the tapered inner sidewall but is spaced apart from the central upper surface.

公开(公告)号：US20190131458A1

公开(公告)日：2019-05-02

申请号：US16004309

申请日：2018-06-08

Applicant: SK hynix Inc.

Inventor： Hyangkeun YOO

IPC: H01L29/78 ,  H01L27/1159 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L27/1159 ,  H01L29/40111 ,  H01L29/516 ,  H01L29/6684 ,  H01L45/04 ,  H01L45/06 ,  H01L45/124 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

Abstract: A ferroelectric memory device according to an embodiment of the present disclosure includes a substrate, a ferroelectric material layer disposed on the substrate, a gate electrode layer disposed on the ferroelectric material layer, and a polarization switching seed layer disposed between the ferroelectric material layer and the gate electrode layer.

公开(公告)号：US20180301625A1

公开(公告)日：2018-10-18

申请号：US15953921

申请日：2018-04-16

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.r.l.

Inventor： Pierre MORIN ,  Michel HAOND ,  Paola ZULIANI

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/126 ,  H01L27/2436 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1608

Abstract: A phase change memory includes an L-shaped resistive element having a first part that extends between a layer of phase change material and an upper end of a conductive via and a second part that rests at least partially on the upper end of the conductive via and may further extend beyond a peripheral edge of the conductive via. The upper part of the conductive via is surrounded by an insulating material that is not likely to adversely react with the metal material of the resistive element.

公开(公告)号：US20180138184A1

公开(公告)日：2018-05-17

申请号：US15804846

申请日：2017-11-06

Applicant: Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

Inventor： Xi LIN ,  Yi Hua SHEN

IPC: H01L27/108 ,  H01L27/24

CPC classification number: H01L27/10879 ,  H01L27/10826 ,  H01L27/2436 ,  H01L28/92 ,  H01L45/04 ,  H01L45/06 ,  H01L45/124 ,  H01L45/16

Abstract: Dynamic random access memory (DRAM) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming an interlayer dielectric layer over the base substrate; forming an opening passing through the interlayer dielectric layer; and forming a memory structure, having a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer, in the opening.

公开(公告)号：US09972779B2

公开(公告)日：2018-05-15

申请号：US14967386

申请日：2015-12-14

Applicant: Winbond Electronics Corp.

Inventor： Frederick Chen ,  Ping-Kun Wang ,  Shao-Ching Liao ,  Po-Yen Hsu ,  Yi-Hsiu Chen ,  Ting-Ying Shen ,  Bo-Lun Wu ,  Meng-Hung Lin

IPC: H01L47/00 ,  H01L45/00

CPC classification number: H01L45/1266 ,  H01L45/08 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/146

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.

公开(公告)号：US09882126B2

公开(公告)日：2018-01-30

申请号：US15095023

申请日：2016-04-09

Applicant: International Business Machines Corporation ,  Macronix International Co., Ltd

Inventor： Matthew J. BrightSky ,  Huai-Yu Cheng ,  Wei-Chih Chien ,  Sangbum Kim ,  Chiao-Wen Yeh

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

Abstract: A phase change storage device, Integrated Circuit (IC) chip including the devices and method of manufacturing IC chips with the devices. The device includes a phase change storage region with multiple phase change regions, e.g., two (2), of different phase change material serially-connected between said program/read line and a select device conduction terminal.

公开(公告)号：US09847479B2

公开(公告)日：2017-12-19

申请号：US15655134

申请日：2017-07-20

Applicant: GULA CONSULTING LIMITED LIABILITY COMPANY

Inventor： Frederick T. Chen ,  Ming-Jinn Tsai

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L45/06 ,  H01L27/24 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/128 ,  H01L45/14 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1691

Abstract: A phase-change memory element is provided. The phase-change memory element may include an electrode; a phase-change material that contacts the electrode; a first conductor that contacts the phase-change material; and a second conductor that contacts the phase-change material. The second conductor may be electrically connected to the first conductor only through the phase-change material, and each of the first and second conductors may be electrically connected to the electrode only through the phase-change material.

公开(公告)号：US09831428B2

公开(公告)日：2017-11-28

申请号：US14972152

申请日：2015-12-17

Applicant: Micron Technology, Inc.

Inventor： Marcello Ravasio ,  Samuele Sciarrillo ,  Andrea Gotti

IPC: H01L45/00 ,  H01L27/105 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/24 ,  H01L27/22

CPC classification number: H01L45/124 ,  H01L21/28 ,  H01L21/3213 ,  H01L27/1052 ,  H01L27/222 ,  H01L27/2427 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/14 ,  H01L45/144 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element. A middle electrode is formed between the memory element and the switch element. An outside electrode is formed adjacent the switch element or the memory element at a location other than between the memory element and the switch element. A lateral dimension of the middle electrode is different than a lateral dimension of the outside electrode.

公开(公告)号：US09825224B2

公开(公告)日：2017-11-21

申请号：US15233028

申请日：2016-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Pei Hsieh ,  Chung-Yen Chou ,  Shih-Chang Liu

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1691 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/149 ,  H01L45/1675

Abstract: The present disclosure relates to an integrated circuit device having an RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a bottom electrode disposed over a lower metal interconnect layer. The integrated circuit device also has a resistance switching layer with a variable resistance located on the bottom electrode, and a top electrode located over the resistance switching layer. The integrated circuit device also has a self-sputtering spacer having a lateral portion that surrounds the bottom electrode at a position that is vertically disposed between the resistance switching layer and a bottom etch stop layer and a vertical portion abutting sidewalls of the resistance switching layer and the top electrode. The integrated circuit device also has a top etch stop layer located over the bottom etch stop layer abutting sidewalls of the self-sputtering spacer and overlying the top electrode.

公开(公告)号：US20170324034A1

公开(公告)日：2017-11-09

申请号：US15661351

申请日：2017-07-27

Applicant: Micron Technology, Inc.

Inventor： Eugene P. Marsh ,  Jun Liu

IPC: H01L45/00

CPC classification number: H01L45/085 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/143 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1683

Abstract: Resistive memory having confined filament formation is described herein. One or more method embodiments include forming an opening in a stack having a silicon material and an oxide material on the silicon material, and forming an oxide material in the opening adjacent the silicon material, wherein the oxide material formed in the opening confines filament formation in the resistive memory cell to an area enclosed by the oxide material formed in the opening.