公开(公告)号：US20090189211A1

公开(公告)日：2009-07-30

申请号：US12020428

申请日：2008-01-25

申请人： Takashi Orimoto ,  George Matamis ,  James Kai

发明人： Takashi Orimoto ,  George Matamis ,  James Kai

IPC分类号： H01L29/788 ,  H01L21/3205

CPC分类号： H01L27/11521 ,  H01L27/11519

摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming are provided. A charge storage layer is etched into strips extending across a substrate surface in a row direction with a tunnel dielectric layer therebetween. The resulting strips may be continuous in the row direction or may comprise individual charge storage regions if already divided along their length in the row direction. A second layer of dielectric material is formed along the sidewalls of the strips and over the tunnel dielectric layer in the spaces therebetween. The second layer is etched into regions overlaying the tunnel dielectric layer in the spaces between strips. An intermediate dielectric layer is formed along exposed portions of the sidewalls of the strips and over the second dielectric layer in the spaces therebetween. A layer of control gate material is deposited in the spaces between strips. The resulting control gates are separated from the strips by the intermediate dielectric layer and from the substrate surface by the tunnel dielectric layer, the second layer of dielectric material and the intermediate dielectric layer.

摘要翻译： 提供了具有双控制栅极存储单元的非易失性半导体存储器件和形成方法。 电荷存储层被蚀刻成沿着行方向延伸穿过衬底表面的条带，其间具有隧道介电层。 所得到的条带可以在行方向上是连续的，或者可以包括单独的电荷存储区域，如果沿着它们的行方向上的长度被划分。 第二层电介质材料沿着条的侧壁和隧道介电层之间的空间形成。 第二层被蚀刻到条带之间的空间中覆盖隧道介电层的区域中。 沿着条的侧壁的暴露部分和在它们之间的空间中的第二介电层上方形成中间介电层。 控制栅极材料层沉积在条带之间的空间中。 所得到的控制栅极通过中间介电层和通过隧道介电层，第二介电材料层和中间介质层从衬底表面与条分离。

公开(公告)号：US20080318381A1

公开(公告)日：2008-12-25

申请号：US11765866

申请日：2007-06-20

申请人： George Matamis ,  James Kai ,  Takashi Orimoto ,  Nima Mokhlesi

发明人： George Matamis ,  James Kai ,  Takashi Orimoto ,  Nima Mokhlesi

IPC分类号： H01L21/8247

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.

摘要翻译： 公开了高密度半导体器件及其制造方法。 利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其可以小于所使用的工艺的最小可光刻解析的元件尺寸。 可以处理第一组间隔件以提供平面和平行的侧壁。 可以在第一组间隔件的平面和平行的侧壁上形成第二组间隔件。 第二组间隔件用作掩模以在第二组间隔物下方的层中形成一个或多个电路元件。 根据本发明的实施例的步骤允许使用递归间隔物技术，其产生要形成的坚固的，均匀间隔的间隔物并用作电路元件的掩模。

公开(公告)号：US07592223B2

公开(公告)日：2009-09-22

申请号：US12061642

申请日：2008-04-02

申请人： Tuan Pham ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  George Matamis

发明人： Tuan Pham ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  George Matamis

IPC分类号： H01L21/8247

CPC分类号： H01L27/11543 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11541

摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated select and peripheral circuitry formation are provided. Strips of charge storage material elongated in a column direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. After forming isolation trenches in the substrate between active areas below the strips of charge storage material, spacer-assisted patterning is used to form a pattern at the memory array region. Strips of photoresist are patterned over a portion of the pattern at the memory array. Photoresist is also applied at the peripheral circuitry region. At least a portion of the layer stack is etched using the photoresist as a mask before removing the photoresist and etching the strips of charge storage material to form the charge storage structures.

摘要翻译： 提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成选择和外围电路形成的方法。 形成沿着柱方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。 在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。 在电荷存储材料条带之下的有源区域中的衬底中形成隔离沟槽之后，使用间隔物辅助图案化以在存储器阵列区域形成图案。 在存储器阵列上的图案的一部分上图案化的光致抗蚀剂条纹。 光刻胶也被应用在外围电路区域。 在去除光致抗蚀剂并蚀刻电荷存储材料条之前，使用光致抗蚀剂作为掩模来蚀刻层叠体的至少一部分，以形成电荷存储结构。

公开(公告)号：US20080268596A1

公开(公告)日：2008-10-30

申请号：US12061642

申请日：2008-04-02

申请人： Tuan Pham ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  George Matamis

发明人： Tuan Pham ,  Takashi Orimoto ,  Masaaki Higashitani ,  James Kai ,  George Matamis

IPC分类号： H01L21/336

CPC分类号： H01L27/11543 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11541

摘要： Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming the same using integrated select and peripheral circuitry formation are provided. Strips of charge storage material elongated in a column direction across the surface of a substrate with strips of tunnel dielectric material therebetween are formed. The strips of charge storage material can include multiple layers of charge storage material to form composite charge storage structures in one embodiment. After forming isolation trenches in the substrate between active areas below the strips of charge storage material, spacer-assisted patterning is used to form a pattern at the memory array region. Strips of photoresist are patterned over a portion of the pattern at the memory array. Photoresist is also applied at the peripheral circuitry region. At least a portion of the layer stack is etched using the photoresist as a mask before removing the photoresist and etching the strips of charge storage material to form the charge storage structures.

摘要翻译： 提供了具有双控制栅极存储器单元的非易失性半导体存储器件及其使用集成选择和外围电路形成的方法。 形成沿着柱方向延伸穿过衬底表面的电荷存储材料带，其间具有隧道介电材料带。 在一个实施例中，电荷存储材料条可以包括多层电荷存储材料以形成复合电荷存储结构。 在电荷存储材料条带之下的有源区域中的衬底中形成隔离沟槽之后，使用间隔物辅助图案化以在存储器阵列区域形成图案。 在存储器阵列上的图案的一部分上图案化的光致抗蚀剂条纹。 光刻胶也被应用在外围电路区域。 在去除光致抗蚀剂并蚀刻电荷存储材料条之前，使用光致抗蚀剂作为掩模来蚀刻层叠体的至少一部分，以形成电荷存储结构。

公开(公告)号：US20080171428A1

公开(公告)日：2008-07-17

申请号：US11623314

申请日：2007-01-15

申请人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

发明人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

IPC分类号： H01L21/3205

CPC分类号： H01L21/32139 ,  H01L21/0337 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

摘要翻译： 提供了高密度半导体器件及其制造方法。 利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。 形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。 具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

公开(公告)号：US08143156B2

公开(公告)日：2012-03-27

申请号：US11765866

申请日：2007-06-20

申请人： George Matamis ,  James Kai ,  Takashi Orimoto ,  Nima Mokhlesi

发明人： George Matamis ,  James Kai ,  Takashi Orimoto ,  Nima Mokhlesi

IPC分类号： H01L21/4763

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11521

摘要： High density semiconductor devices and methods of fabricating the same are disclosed. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which may be smaller than the smallest lithographically resolvable element size of the process being used. A first set of spacers may be processed to provide planar and parallel sidewalls. A second set of spacers may be formed on planar and parallel sidewalls of the first set of spacers. The second set of spacers serve as a mask to form one or more circuit elements in a layer beneath the second set of spacers. The steps according to embodiments of the invention allow a recursive spacer technique to be used which results in robust, evenly spaced, spacers to be formed and used as masks for the circuit elements.

摘要翻译： 公开了高密度半导体器件及其制造方法。 利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其可以小于所使用的工艺的最小可光刻解析的元件尺寸。 可以处理第一组间隔件以提供平面和平行的侧壁。 可以在第一组间隔件的平面和平行的侧壁上形成第二组间隔件。 第二组间隔件用作掩模以在第二组间隔物下方的层中形成一个或多个电路元件。 根据本发明的实施例的步骤允许使用递归间隔物技术，其产生要形成的坚固的，均匀间隔的间隔物并用作电路元件的掩模。

公开(公告)号：US07960266B2

公开(公告)日：2011-06-14

申请号：US12791103

申请日：2010-06-01

申请人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

发明人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

摘要翻译： 提供了高密度半导体器件及其制造方法。 利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻可分辨的元件尺寸。 形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。 具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

公开(公告)号：US07704832B2

公开(公告)日：2010-04-27

申请号：US12058512

申请日：2008-03-28

申请人： James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  George Matamis ,  Takashi Orimoto

发明人： James Kai ,  Tuan Pham ,  Masaaki Higashitani ,  George Matamis ,  Takashi Orimoto

IPC分类号： H01L21/8247

CPC分类号： H01L27/11529 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11536 ,  H01L27/11539

摘要： Non-volatile memory and integrated memory and peripheral circuitry fabrication processes are provided. Sets of charge storage regions, such as NAND strings including multiple non-volatile storage elements, are formed over a semiconductor substrate using a layer of charge storage material such as a first layer of polysilicon. An intermediate dielectric layer is provided over the charge storage regions. A layer of conductive material such as a second layer of polysilicon is deposited over the substrate and etched to form the control gates for the charge storage regions and the gate regions of the select transistors for the sets of storage elements. The first layer of polysilicon is removed from a portion of the substrate, facilitating fabrication of the select transistor gate regions from only the second layer of polysilicon. Peripheral circuitry formation is also incorporated into the fabrication process to form the gate regions for devices such as high voltage and logic transistors. The gate regions of these devices can be formed from the layer forming the control gates of the memory array.

摘要翻译： 提供非易失性存储器和集成存储器和外围电路制造工艺。 使用诸如第一多晶硅层的电荷存储材料层在半导体衬底上形成诸如包括多个非易失性存储元件的NAND串的电荷存储区的集合。 中间电介质层设置在电荷存储区域的上方。 将诸如第二多晶硅层的导电材料层沉积在衬底上并被蚀刻以形成用于存储元件组的选择晶体管的电荷存储区域和栅极区域的控制栅极。 从衬底的一部分去除第一层多晶硅，便于仅从第二层多晶硅制造选择晶体管栅极区。 外围电路形成也被并入到制造过程中以形成诸如高电压和逻辑晶体管的器件的栅极区域。 这些器件的栅极区域可以由形成存储器阵列的控制栅极的层形成。

公开(公告)号：US20100240182A1

公开(公告)日：2010-09-23

申请号：US12791103

申请日：2010-06-01

申请人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

发明人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

摘要翻译： 提供了高密度半导体器件及其制造方法。 利用间隔制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小光刻可分辨元件尺寸。 形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。 具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。

公开(公告)号：US07773403B2

公开(公告)日：2010-08-10

申请号：US11623315

申请日：2007-01-15

申请人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

发明人： James Kai ,  George Matamis ,  Tuan Duc Pham ,  Masaaki Higashitani ,  Takashi Orimoto

IPC分类号： G11C5/06

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： High density semiconductor devices and methods of fabricating the same are provided. Spacer fabrication techniques are utilized to form circuit elements having reduced feature sizes, which in some instances are smaller than the smallest lithographically resolvable element size of the process being used. Spacers are formed that serve as a mask for etching one or more layers beneath the spacers. An etch stop pad layer having a material composition substantially similar to the spacer material is provided between a dielectric layer and an insulating sacrificial layer such as silicon nitride. When etching the sacrificial layer, the matched pad layer provides an etch stop to avoid damaging and reducing the size of the dielectric layer. The matched material compositions further provide improved adhesion for the spacers, thereby improving the rigidity and integrity of the spacers.

摘要翻译： 提供了高密度半导体器件及其制造方法。 利用间隔器制造技术来形成具有减小的特征尺寸的电路元件，其在一些情况下小于正在使用的工艺的最小可光刻解析的元件尺寸。 形成隔板，其用作蚀刻间隔物下面的一个或多个层的掩模。 具有与间隔物材料基本相似的材料组成的蚀刻停止垫层设置在电介质层和诸如氮化硅的绝缘牺牲层之间。 当蚀刻牺牲层时，匹配的焊盘层提供蚀刻停止以避免损坏并减小电介质层的尺寸。 匹配的材料组合物还提供了用于间隔物的改进的粘合性，从而提高了间隔物的刚度和完整性。