公开(公告)号：US20120193701A1

公开(公告)日：2012-08-02

申请号：US13101155

申请日：2011-05-05

Applicant: Wei-Chieh Lin

Inventor： Wei-Chieh Lin

IPC: H01L27/06 ,  H01L21/8234

CPC classification number: H01L29/7813 ,  H01L27/0248 ,  H01L27/0255 ,  H01L27/0259 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808

Abstract: A power semiconductor device with an electrostatic discharge (ESD) structure includes an N-type semiconductor substrate, at least one ESD device, and at least one trench type transistor device. The N-type semiconductor has at least two trenches, and the ESD device is disposed in the N-type semiconductor substrate between the trenches. The ESD device includes a P-type first doped region, and an N-type second doped region and an N-type third doped region disposed in the P-type first doped region. The N-type second doped region is electrically connected to a gate of the trench type transistor device, and the N-type third doped region is electrically connected to a drain of the trench type transistor device.

Abstract translation: 具有静电放电（ESD）结构的功率半导体器件包括N型半导体衬底，至少一个ESD器件和至少一个沟槽型晶体管器件。 N型半导体具有至少两个沟槽，并且ESD元件设置在沟槽之间的N型半导体衬底中。 ESD器件包括P型第一掺杂区域和设置在P型第一掺杂区域中的N型第二掺杂区域和N型第三掺杂区域。 N型第二掺杂区域电连接到沟槽型晶体管器件的栅极，并且N型第三掺杂区域电连接到沟槽型晶体管器件的漏极。

公开(公告)号：US20120139037A1

公开(公告)日：2012-06-07

申请号：US13091160

申请日：2011-04-21

Applicant: Wei-Chieh Lin ,  Jia-Fu Lin

Inventor： Wei-Chieh Lin ,  Jia-Fu Lin

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7828 ,  H01L21/26586 ,  H01L29/41766 ,  H01L29/66666

Abstract: A manufacturing method of a depletion mode trench semiconductor device includes following steps. Firstly, a substrate including a drift epitaxial layer disposed thereon is provided. A trench is disposed in the drift epitaxial layer. A gate dielectric layer is formed on an inner sidewall of the trench and an upper surface of the drift epitaxial layer. A base doped region is formed in the drift epitaxial layer and adjacent to a side of the trench. A thin doped region is formed and conformally contacts the gate dielectric layer. A gate material layer is formed to fill the trench. A source doped region is formed in the base doped region, and the source doped region overlaps the thin doped region at a side of the trench. Finally, a contact doped region is formed to overlap the thin doped region, and the contact doped region is adjacent to the source doped region.

Abstract translation: 耗尽型沟槽半导体器件的制造方法包括以下步骤。 首先，提供包括设置在其上的漂移外延层的衬底。 沟槽设置在漂移外延层中。 栅极电介质层形成在沟槽的内侧壁和漂移外延层的上表面上。 基极掺杂区域形成在漂移外延层中并与沟槽的一侧相邻。 形成薄的掺杂区域并保形地接触栅极电介质层。 形成栅极材料层以填充沟槽。 源极掺杂区域形成在基极掺杂区域中，并且源极掺杂区域与沟槽侧面的薄掺杂区域重叠。 最后，形成接触掺杂区域以与薄掺杂区域重叠，并且接触掺杂区域与源极掺杂区域相邻。

公开(公告)号：US20120049263A1

公开(公告)日：2012-03-01

申请号：US13008908

申请日：2011-01-19

Applicant: Wei-Chieh Lin

Inventor： Wei-Chieh Lin

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L28/60 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7811

Abstract: A semiconductor device includes a semiconductor substrate having a conductive type, a source metal layer, a gate metal layer, at least one transistor device, a heavily doped region having the conductive type, a capacitor dielectric layer, a conductive layer. The source metal layer and the gate metal layer are disposed on the semiconductor substrate. The transistor device is disposed in the semiconductor substrate under the source metal layer. The heavily doped region, the capacitor dielectric layer and the conductive layer constitute a capacitor structure, disposed under the gate metal layer, and the capacitor structure is electrically connected between a source and a drain of the transistor device.

Abstract translation: 半导体器件包括具有导电类型的半导体衬底，源极金属层，栅极金属层，至少一个晶体管器件，具有导电类型的重掺杂区域，电容器介电层，导电层。 源极金属层和栅极金属层设置在半导体衬底上。 晶体管器件设置在源极金属层下面的半导体衬底中。 重掺杂区域，电容器介电层和导电层构成电容器结构，设置在栅极金属层下方，并且电容器结构电连接在晶体管器件的源极和漏极之间。

公开(公告)号：US20110084334A1

公开(公告)日：2011-04-14

申请号：US12615271

申请日：2009-11-10

Applicant: Wei-Chieh Lin ,  Jen-Hao Yeh ,  Jia-Fu Lin ,  Chia-Hui Chen

Inventor： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Jia-Fu Lin ,  Chia-Hui Chen

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66727 ,  H01L29/66734

Abstract: A bilateral conduction semiconductor device and a manufacturing method thereof are provided. The bilateral conduction semiconductor device includes an epitaxial layer having a first conductive type and a first trench, a first gate conductive layer disposed on a sidewall of the first trench, a second gate conductive layer disposed opposite to the first gate conductive layer, and a doped region having the first conductive type. The doped region is disposed in the epitaxial layer between the first gate conductive layer and the second gate conductive layer, and a doped concentration of the doped region is larger than a doped concentration of the epitaxial layer.

Abstract translation: 提供了一种双向传导半导体器件及其制造方法。 双向传导半导体器件包括具有第一导电类型和第一沟槽的外延层，设置在第一沟槽的侧壁上的第一栅极导电层，与第一栅极导电层相对设置的第二栅极导电层和掺杂 区域具有第一导电类型。 掺杂区域设置在第一栅极导电层和第二栅极导电层之间的外延层中，掺杂区域的掺杂浓度大于外延层的掺杂浓度。

公开(公告)号：US20110079819A1

公开(公告)日：2011-04-07

申请号：US12615278

申请日：2009-11-10

Applicant: Wei-Chieh Lin ,  Jen-Hao Yeh ,  Ho-Tai Chen

Inventor： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Ho-Tai Chen

IPC: H01L29/739 ,  H01L21/331

CPC classification number: H01L29/7397 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/66348

Abstract: An IGBT with a fast reverse recovery time rectifier includes an N-type drift epitaxial layer, a gate, a gate insulating layer, a P-type doped base region, an N-type doped source region, a P-type doped contact region, and a P-type lightly doped region. The P-type doped base region is disposed in the N-type drift epitaxial layer, and the P-type doped contact region is disposed in the N-type drift epitaxial layer. The P-type lightly doped region is disposed between the P-type contact doped region and the N-type drift epitaxial layer, and is in contact with the N-type drift epitaxial layer.

Abstract translation: 具有快速反向恢复时间整流器的IGBT包括N型漂移外延层，栅极，栅极绝缘层，P型掺杂基极区域，N型掺杂源极区域，P型掺杂接触区域， 和P型轻掺杂区域。 P型掺杂基区设置在N型漂移外延层中，P型掺杂接触区设置在N型漂移外延层中。 P型轻掺杂区域设置在P型接触掺杂区域和N型漂移外延层之间，并与N型漂移外延层接触。

公开(公告)号：US07867854B2

公开(公告)日：2011-01-11

申请号：US12507808

申请日：2009-07-23

Applicant: Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Guo-Liang Yang ,  Jen-Hao Yeh

Inventor： Wei-Chieh Lin ,  Hsin-Yu Hsu ,  Guo-Liang Yang ,  Jen-Hao Yeh

IPC: H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: Wider and narrower trenches are formed in a substrate. A first gate material layer is deposited but not fully fills the wider trench. The first gate material layer in the wider trench and above the substrate original surface is removed by isotropic or anisotropic etching back. A first dopant layer is formed in the surface layer of the substrate at the original surface and the sidewall and bottom of the wider trench by tilt ion implantation. A second gate material layer is deposited to fully fill the trenches. The gate material layer above the original surface is removed by anisotropic etching back. A second dopant layer is formed in the surface layer of the substrate at the original surface by ion implantation. The dopants are driven-in to form a base in the substrate and a bottom-lightly-doped layer surrounding the bottom of the wider trench and adjacent to the base.

Abstract translation: 在衬底中形成更宽且更窄的沟槽。 沉积第一栅极材料层，但不完全填充较宽的沟槽。 通过各向同性或各向异性蚀刻来去除较宽沟槽中的第一栅极材料层和衬底原始表面之上。 第一掺杂剂层通过倾斜离子注入在原始表面和较宽沟槽的侧壁和底部形成在衬底的表面层中。 沉积第二栅极材料层以完全填充沟槽。 通过各向异性蚀刻去除原始表面上方的栅极材料层。 通过离子注入在原始表面的基板的表面层中形成第二掺杂剂层。 掺杂剂被驱入以在衬底中形成基底，并且围绕较宽沟槽的底部并且与基底相邻的底部轻掺杂层。