公开(公告)号：US08774042B2

公开(公告)日：2014-07-08

申请号：US13441003

申请日：2012-04-06

申请人： Ting-Kang Chang ,  Po-Wei Liu ,  Jui-Chiang Wang ,  Jen-Hao Yeh

发明人： Ting-Kang Chang ,  Po-Wei Liu ,  Jui-Chiang Wang ,  Jen-Hao Yeh

IPC分类号： H04L12/26

CPC分类号： H04B10/0795 ,  H04L25/0262

摘要： A communication apparatus with transmitted rate detecting function and the method therefore is provided. The communication apparatus receives an input signal transmitted at a first rate or a second rate from a remote apparatus. The method includes setting the communication apparatus to operate at an initial receiving rate; sampling the input signal by a specific sampling frequency to generate a sample result; estimating the input transmitted rate of the input signal according to the sample result so as to set the receiving rate of the communication apparatus at a working rate; and communicating with the remote apparatus at the working rate. The second rate is higher than the first rate, and the specific sampling frequency is associated with the initial receiving rate.

摘要翻译： 提供了一种具有传输速率检测功能的通信设备及其方法。 通信装置从远程装置接收以第一速率或第二速率发送的输入信号。 该方法包括将通信设备设置为以初始接收速率操作; 以特定采样频率对输入信号进行采样以产生采样结果; 根据采样结果估计输入信号的输入传输速率，以将通信设备的接收速率设定为工作速率; 并以工作速率与远程设备通信。 第二速率高于第一速率，具体采样频率与初始接收速率相关。

公开(公告)号：US08704279B2

公开(公告)日：2014-04-22

申请号：US13481462

申请日：2012-05-25

申请人： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

发明人： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC分类号： H01L29/80

CPC分类号： H01L29/7832 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H03K17/223

摘要： A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

摘要翻译： 一种器件包括掩埋阱区和第一导电性的第一HVW区，以及位于第一HVW区上的绝缘区。 第一导电类型的漏极区域设置在绝缘区域的第一侧和第一HVW区域的顶表面区域中。 与第一导电类型相反的第二导电类型的第一阱区和第二阱区在绝缘区的第二侧上。 第一导电类型的第二HVW区域设置在第一和第二阱区域之间，其中第二HVW区域连接到掩埋阱区域。 第一导电类型的源极区域位于第二HVW区域的顶表面区域中，其中源极区域，漏极区域和掩埋阱区域形成JFET。

公开(公告)号：US08624322B1

公开(公告)日：2014-01-07

申请号：US13551262

申请日：2012-07-17

申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Jen-Hao Yeh ,  Chun-Wei Hsu

发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Jen-Hao Yeh ,  Chun-Wei Hsu

IPC分类号： H01L23/62 ,  H01L21/8234

CPC分类号： H01L27/0629

摘要： Provided is a high voltage semiconductor device. The high voltage semiconductor device includes a transistor having a gate, a source, and a drain. The source and the drain are formed in a doped substrate and are separated by a drift region of the substrate. The gate is formed over the drift region and between the source and the drain. The transistor is configured to handle high voltage conditions that are at least a few hundred volts. The high voltage semiconductor device includes a dielectric structure formed between the source and the drain of the transistor. The dielectric structure protrudes into and out of the substrate. Different parts of the dielectric structure have uneven thicknesses. The high voltage semiconductor device includes a resistor formed over the dielectric structure. The resistor has a plurality of winding segments that are substantially evenly spaced apart.

摘要翻译： 提供高压半导体器件。 高电压半导体器件包括具有栅极，源极和漏极的晶体管。 源极和漏极形成在掺杂衬底中并且由衬底的漂移区域分离。 栅极形成在漂移区域上以及源极和漏极之间。 晶体管被配置为处理至少几百伏特的高电压条件。 高电压半导体器件包括在晶体管的源极和漏极之间形成的电介质结构。 电介质结构突出进出基板。 电介质结构的不同部分具有不均匀的厚度。 高电压半导体器件包括在电介质结构上形成的电阻器。 电阻器具有大致均匀间隔开的多个绕组段。

公开(公告)号：US20130313617A1

公开(公告)日：2013-11-28

申请号：US13481462

申请日：2012-05-25

申请人： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

发明人： Jen-Hao Yeh ,  Chih-Chang Cheng ,  Ru-Yi Su ,  Ker Hsiao Huo ,  Po-Chih Chen ,  Fu-Chih Yang ,  Chun Lin Tsai

IPC分类号： H01L29/80

CPC分类号： H01L29/7832 ,  H01L29/0692 ,  H01L29/404 ,  H01L29/41758 ,  H01L29/42356 ,  H01L29/66893 ,  H01L29/66901 ,  H01L29/808 ,  H03K17/223

摘要： A device includes a buried well region and a first HVW region of the first conductivity, and an insulation region over the first HVW region. A drain region of the first conductivity type is disposed on a first side of the insulation region and in a top surface region of the first HVW region. A first well region and a second well region of a second conductivity type opposite the first conductivity type are on the second side of the insulation region. A second HVW region of the first conductivity type is disposed between the first and the second well regions, wherein the second HVW region is connected to the buried well region. A source region of the first conductivity type is in a top surface region of the second HVW region, wherein the source region, the drain region, and the buried well region form a JFET.

摘要翻译： 一种器件包括掩埋阱区和第一导电性的第一HVW区，以及位于第一HVW区上的绝缘区。 第一导电类型的漏极区域设置在绝缘区域的第一侧和第一HVW区域的顶表面区域中。 与第一导电类型相反的第二导电类型的第一阱区和第二阱区在绝缘区的第二侧上。 第一导电类型的第二HVW区域设置在第一和第二阱区域之间，其中第二HVW区域连接到掩埋阱区域。 第一导电类型的源极区域位于第二HVW区域的顶表面区域中，其中源极区域，漏极区域和掩埋阱区域形成JFET。

公开(公告)号：US08384682B2

公开(公告)日：2013-02-26

申请号：US12649357

申请日：2009-12-30

申请人： Hung-Lieh Hu ,  Chun-Hsing Lee ,  Jen-Hao Yeh ,  Sheng-Ho Huang ,  Yuan-Ching Chen ,  Yu-Ming Huang

发明人： Hung-Lieh Hu ,  Chun-Hsing Lee ,  Jen-Hao Yeh ,  Sheng-Ho Huang ,  Yuan-Ching Chen ,  Yu-Ming Huang

IPC分类号： G06F3/41

CPC分类号： G06F3/0386 ,  G06F3/0412 ,  G06F3/0421 ,  G06F2203/04109

摘要： An optical interactive panel includes a cladding layer, a first waveguide array, a second waveguide array, a first set of image sensor, and a second set of image sensor. The cladding layer has a first index of refraction. The first waveguide array has first waveguide channels formed on the cladding layer, wherein the first waveguide channels have a second index of refraction less than the first index of refraction, and extending at a first direction. The second waveguide array has second waveguide channels, formed on the cladding layer and extending at a second direction. The first set of image sensor detects a first set of light signals from the first waveguide channels to determine a first-direction location. The second set of image sensor detects a second set of light signals from the second waveguide channels to determine a second-direction location.

摘要翻译： 光学交互式面板包括包层，第一波导阵列，第二波导阵列，第一组图像传感器和第二组图像传感器。 包层具有第一折射率。 第一波导阵列具有形成在包覆层上的第一波导通道，其中第一波导通道具有小于第一折射率的第二折射率并且沿第一方向延伸。 第二波导阵列具有形成在包覆层上并在第二方向延伸的第二波导通道。 第一组图像传感器检测来自第一波导通道的第一组光信号以确定第一方向位置。 第二组图像传感器检测来自第二波导通道的第二组光信号以确定第二方向位置。

公开(公告)号：US08198684B2

公开(公告)日：2012-06-12

申请号：US12614434

申请日：2009-11-08

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

IPC分类号： H01L23/62

CPC分类号： H01L27/0629 ,  H01L23/60 ,  H01L24/05 ,  H01L27/0255 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.

摘要翻译： 具有漏极电压保护的功率半导体器件包括半导体衬底，至少沟槽栅极晶体管器件和至少沟槽ESD保护器件。 半导体衬底的上表面具有第一沟槽和第二沟槽。 沟槽栅极晶体管器件设置在第一沟槽和半导体衬底中。 沟槽ESD保护器件设置在第二沟槽中，并且包括第一掺杂区，第二掺杂区和第三掺杂区。 第一掺杂区域和第三掺杂区域分别电连接到沟槽栅极晶体管器件的漏极和栅极。

公开(公告)号：US20110084335A1

公开(公告)日：2011-04-14

申请号：US12614434

申请日：2009-11-08

申请人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

发明人： Wei-Chieh Lin ,  Guo-Liang Yang ,  Jen-Hao Yeh ,  Jia-Fu Lin

IPC分类号： H01L27/06 ,  H01L21/8234 ,  H01L23/60

CPC分类号： H01L27/0629 ,  H01L23/60 ,  H01L24/05 ,  H01L27/0255 ,  H01L2924/12035 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

摘要： A power semiconductor device with drain voltage protection includes a semiconductor substrate, at least a trench gate transistor device and at least a trench ESD protection device. An upper surface of the semiconductor substrate has a first trench and a second trench. The trench gate transistor device is disposed in the first trench and the semiconductor substrate. The trench ESD protection device is disposed in the second trench, and includes a first doped region, a second doped region and a third doped region. The first doped region and the third doped region are respectively electrically connected to a drain and a gate of the trench gate transistor device.

摘要翻译： 具有漏极电压保护的功率半导体器件包括半导体衬底，至少沟槽栅极晶体管器件和至少沟槽ESD保护器件。 半导体衬底的上表面具有第一沟槽和第二沟槽。 沟槽栅极晶体管器件设置在第一沟槽和半导体衬底中。 沟槽ESD保护器件设置在第二沟槽中，并且包括第一掺杂区，第二掺杂区和第三掺杂区。 第一掺杂区域和第三掺杂区域分别电连接到沟槽栅极晶体管器件的漏极和栅极。

公开(公告)号：US08168480B2

公开(公告)日：2012-05-01

申请号：US12563172

申请日：2009-09-21

申请人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

发明人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

IPC分类号： H01L21/332

CPC分类号： H01L29/7395 ,  H01L29/0834 ,  H01L29/66333

摘要： An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

摘要翻译： IGBT和二极管的集成结构包括多个掺杂的阴极区域，并且提供其形成方法。 掺杂阴极区域堆叠在半导体衬底中，彼此重叠并接触。 与其他掺杂阴极区域相比，掺杂阴极区域越高，掺杂阴极区域的注入面积越大。 掺杂阴极区域和半导体衬底具有不同的导电类型，并且被施加作为二极管的阴极和IGBT的集电极。 堆叠的掺杂阴极区域可以增加阴极的薄度，并且防止晶片过度变薄和破裂。

公开(公告)号：US08120100B2

公开(公告)日：2012-02-21

申请号：US12616770

申请日：2009-11-11

申请人： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

发明人： Wei-Chieh Lin ,  Jen-Hao Yeh ,  Guo-Liang Yang ,  Jia-Fu Lin

IPC分类号： H01L27/108 ,  H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734

摘要： An overlapping trench gate semiconductor device includes a semiconductor substrate, a plurality of shallow trenches disposed on the semiconductor substrate, a first conductive layer disposed in the shallow trenches, a plurality of deep trenches respectively disposed in each shallow trench, a second conductive layer disposed in the deep trenches, a source metal layer and a gate metal layer. Each of the deep trenches extends into the semiconductor substrate under each shallow trench. The source metal layer is electrically connected to the second conductive layer, and the gate metal layer is electrically connected to the first conductive layer.

摘要翻译： 重叠沟槽栅极半导体器件包括半导体衬底，设置在半导体衬底上的多个浅沟槽，设置在浅沟槽中的第一导电层，分别设置在每个浅沟槽中的多个深沟槽，设置在第二导电层中的第二导电层 深沟槽，源极金属层和栅极金属层。 每个深沟槽在每个浅沟槽下延伸到半导体衬底中。 源极金属层电连接到第二导电层，并且栅极金属层电连接到第一导电层。

公开(公告)号：US20100301386A1

公开(公告)日：2010-12-02

申请号：US12563172

申请日：2009-09-21

申请人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

发明人： Wei-Chieh Lin ,  Ho-Tai Chen ,  Jen-Hao Yeh ,  Li-Cheng Lin ,  Shih-Chieh Hung

IPC分类号： H01L27/06 ,  H01L21/77

CPC分类号： H01L29/7395 ,  H01L29/0834 ,  H01L29/66333

摘要： An integrated structure of an IGBT and a diode includes a plurality of doped cathode regions, and a method of forming the same is provided. The doped cathode regions are stacked in a semiconductor substrate, overlapping and contacting with each other. As compared with other doped cathode regions, the higher a doped cathode region is disposed, the larger implantation area the doped cathode region has. The doped cathode regions and the semiconductor substrate have different conductive types, and are applied as a cathode of the diode and a collector of the IGBT. The stacked doped cathode regions can increase the thinness of the cathode, and prevent the wafer from being overly thinned and broken.

摘要翻译： IGBT和二极管的集成结构包括多个掺杂的阴极区域，并且提供其形成方法。 掺杂阴极区域堆叠在半导体衬底中，彼此重叠并接触。 与其他掺杂阴极区域相比，掺杂阴极区域越高，掺杂阴极区域的注入面积越大。 掺杂阴极区域和半导体衬底具有不同的导电类型，并且被施加作为二极管的阴极和IGBT的集电极。 堆叠的掺杂阴极区域可以增加阴极的薄度，并且防止晶片过度变薄和破裂。