-
公开(公告)号:US20190004700A1
公开(公告)日:2019-01-03
申请号:US15636496
申请日:2017-06-28
Applicant: Western Digital Technologies, Inc.
Inventor: Hadas Oshinsky , Rotem Sela , Amir Shaharabany
CPC classification number: G06F3/061 , G06F3/0608 , G06F3/064 , G06F3/0659 , G06F3/0679 , G06F3/0688 , G06F12/0246 , G06F2212/7201
Abstract: A controller addresses portions of non-volatile memory via a memory interface using physical addresses and addresses portions of host data via the host interface using logical addresses. The controller maintains logical to physical mappings and physical to logical mappings for the logical addresses and the physical addresses. The controller is configured to move data from a source logical address to a destination logical address by updating logical to physical mappings and physical address to logical mappings without instructing the non-volatile memory to move the data between physical locations. In one embodiment, this process is used to implement a command to move or defragment data.
-
公开(公告)号:US20240143509A1
公开(公告)日:2024-05-02
申请号:US18222034
申请日:2023-07-14
Applicant: Western Digital Technologies, Inc.
Inventor: Rotem Sela , Hadas Oshinsky , Einav Zilberstein
IPC: G06F12/0873 , G06F12/02 , G06F12/123
CPC classification number: G06F12/0873 , G06F12/0253 , G06F12/123
Abstract: Zoned memory typically requires write commands to be sent from a host to a data storage device in logical block address (LBA) sequential order. Instead of rejecting out-of-order write commands, the data storage device can execute those commands and internally deal with the out-of-order problem. For example, the data storage device can use a special zone logical-to-physical address table, use a temporary zone data buffer, and/or store a data's LBA in a header for later matching.
-
43.
公开(公告)号:US20230195376A1
公开(公告)日:2023-06-22
申请号:US17558089
申请日:2021-12-21
Applicant: Western Digital Technologies, Inc.
Inventor: Einav Zilberstein , Hadas Oshinsky , Oren Ben Hayun , Rotem Sela , Alex Lemberg
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/064 , G06F3/0619 , G06F3/0673
Abstract: A storage system analyzes a logical block address range of data in a resolution of a defragmentation unit. The storage system determines whether a given defragmentation unit is fragmented above a threshold and performs a defragmentation operation accordingly. Additionally or alternatively, the storage system can receive a suggested logical block address read order from a host to improve performance.
-
公开(公告)号:US11675512B2
公开(公告)日:2023-06-13
申请号:US17878253
申请日:2022-08-01
Applicant: Western Digital Technologies, Inc.
Inventor: Rotem Sela , Einav Zilberstein , Karin Inbar
IPC: G06F3/06 , G06F12/1009 , G06F12/0888 , G11C11/56
CPC classification number: G06F3/064 , G06F3/0604 , G06F3/0673 , G06F12/0888 , G06F12/1009 , G06F2212/657 , G11C11/5621 , G11C11/5671
Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
-
公开(公告)号:US11537320B2
公开(公告)日:2022-12-27
申请号:US16780216
申请日:2020-02-03
Applicant: Western Digital Technologies, Inc.
Inventor: Rotem Sela , Amir Shaharabany , Eliad Adi Klein
IPC: G06F3/06 , G06F12/10 , G06F21/60 , G06F1/3296
Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from the host that is recognized by the storage system as a read host memory command; in response to receiving the write command, send an identification of a location in the host memory to the host; and receive, from the host, data that is stored in the location in the host memory. Other embodiments are provided.
-
公开(公告)号:US20220365679A1
公开(公告)日:2022-11-17
申请号:US17878253
申请日:2022-08-01
Applicant: Western Digital Technologies, Inc.
Inventor: Rotem Sela , Einav Zilberstein , Karin Inbar
IPC: G06F3/06 , G06F12/1009
Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
-
公开(公告)号:US20220229555A1
公开(公告)日:2022-07-21
申请号:US17183703
申请日:2021-02-24
Applicant: Western Digital Technologies, Inc.
Inventor: Rotem Sela , Einav Zilberstein , Karin Inbar
IPC: G06F3/06 , G06F12/1009
Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer and/or a read buffer. When the storage system uses the SLC blocks as a read buffer, the storage system reads data from multi-level cell (MLC) blocks in the memory and stores the data in the read buffer prior to receiving a read command from a host for the data. When the storage system uses the SLC blocks as a write buffer, the storage system retains certain data in the write buffer while other data is flushed from the write buffer to MLC blocks in the memory.
-
公开(公告)号:US11327684B2
公开(公告)日:2022-05-10
申请号:US16874101
申请日:2020-05-14
Applicant: Western Digital Technologies, Inc.
Inventor: Rotem Sela , Amir Shaharabany , Eliad Adi Klein
Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
-
公开(公告)号:US20210357148A1
公开(公告)日:2021-11-18
申请号:US16874101
申请日:2020-05-14
Applicant: Western Digital Technologies, Inc.
Inventor: Rotem Sela , Amir Shaharabany , Eliad Adi Klein
Abstract: A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.
-
公开(公告)号:US11088845B2
公开(公告)日:2021-08-10
申请号:US16267040
申请日:2019-02-04
Applicant: Western Digital Technologies, Inc.
Inventor: Rotem Sela , Miki Sapir
Abstract: An apparatus includes a Replay Protected Memory Block (RPMB) formed in a plurality of non-volatile memory cells. Control circuitry is configured to authenticate access to the RPMB with a plurality of keys. Authentication of write access to the RPMB is through a write key and authentication of read access to the RPMB is through a read key.
-
-
-
-
-
-
-
-
-