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    Dual slc/qlc programming and resource releasing
    1.
    发明授权
    Dual slc/qlc programming and resource releasing 有权

    公开(公告)号：US11837277B2

    公开(公告)日：2023-12-05

    申请号：US17455696

    申请日：2021-11-19

    申请人： Western Digital Technologies, Inc.

    发明人： Karin Inbar ,  Shay Benisty

    IPC分类号： G11C11/40 ,  G11C11/4093 ,  G11C11/56 ,  G06F13/16 ,  G06F11/07

    CPC分类号： G11C11/4093 ,  G06F11/076 ,  G06F13/1673 ,  G11C11/5628 ,  G11C11/5642 ,  G11C2211/5641

    摘要： The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to QLC with the data read from SLC and then a fine write to QLC with data re-read from SLC, the foggy write to QLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to QLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to QLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough.

    NON-VOLATILE MEMORY DIE WITH DEEP LEARNING NEURAL NETWORK
    2.
    发明申请
    NON-VOLATILE MEMORY DIE WITH DEEP LEARNING NEURAL NETWORK 有权

    公开(公告)号：US20210375358A1

    公开(公告)日：2021-12-02

    申请号：US17405923

    申请日：2021-08-18

    申请人： Western Digital Technologies, Inc.

    发明人： Rami Rom ,  Ofir Pele ,  Alexander Bazarsky ,  Tomer Tzvi Eliash ,  Ran Zamir ,  Karin Inbar

    IPC分类号： G11C11/56 ,  G06N3/08 ,  G06N3/063

    摘要： Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

    NON-VOLATILE MEMORY DIE WITH DEEP LEARNING NEURAL NETWORK
    3.
    发明申请
    NON-VOLATILE MEMORY DIE WITH DEEP LEARNING NEURAL NETWORK 审中-公开

    公开(公告)号：US20200185027A1

    公开(公告)日：2020-06-11

    申请号：US16212596

    申请日：2018-12-06

    申请人： Western Digital Technologies, Inc.

    发明人： Rami Rom ,  Ofir Pele ,  Alexander Bazarsky ,  Tomer Tzvi Eliash ,  Ran Zamir ,  Karin Inbar

    IPC分类号： G11C11/56 ,  G06N3/063 ,  G06N3/08

    摘要： Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

    NON-VOLATILE MEMORY DIE WITH DEEP LEARNING NEURAL NETWORK
    4.
    发明申请
    NON-VOLATILE MEMORY DIE WITH DEEP LEARNING NEURAL NETWORK 审中-公开

    公开(公告)号：US20200184335A1

    公开(公告)日：2020-06-11

    申请号：US16212586

    申请日：2018-12-06

    申请人： Western Digital Technologies, Inc.

    发明人： Rami Rom ,  Ofir Pele ,  Alexander Bazarsky ,  Tomer Tzvi Eliash ,  Ran Zamir ,  Karin Inbar

    IPC分类号： G06N3/08 ,  G06N3/04 ,  G06N3/063

    摘要： Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

    DETECTION OF DATA STORAGE DEVICE REMOVAL
    5.
    发明公开
    DETECTION OF DATA STORAGE DEVICE REMOVAL 审中-公开

    公开(公告)号：US20240354451A1

    公开(公告)日：2024-10-24

    申请号：US18225630

    申请日：2023-07-24

    申请人： Western Digital Technologies, Inc.

    发明人： Avichay Hodes ,  Karin Inbar ,  Alexander Bazarsky

    IPC分类号： G06F21/85 ,  G06F21/72

    CPC分类号： G06F21/85 ,  G06F21/72

    摘要： Detecting the removal of a data storage device from a storage system involves first determining that a shorter pin of an electrical connector of a storage device is disconnected from a mating electrical connector, such as by sensing a voltage drop on that pin, then determining at a later time that a longer pin of the connector is disconnected from the mating connector. Responsive to determining that the longer pin was disconnected after a predetermined period of time after the shorter pin, a conclusion may be made that the storage device has been removed from the system as opposed to being subject to a simple device power aberration. Thus, responsive data destruction action(s) may be taken to render the data stored on the device inaccessible to the attacker thereby protecting the device even after the device is removed from the storage system.

    Non-volatile memory die with deep learning neural network
    7.
    发明授权
    Non-volatile memory die with deep learning neural network 有权

    公开(公告)号：US11705191B2

    公开(公告)日：2023-07-18

    申请号：US17405923

    申请日：2021-08-18

    申请人： Western Digital Technologies, Inc.

    发明人： Rami Rom ,  Ofir Pele ,  Alexander Bazarsky ,  Tomer Tzvi Eliash ,  Ran Zamir ,  Karin Inbar

    IPC分类号： G11C11/56 ,  G06N3/084 ,  G06N3/063

    CPC分类号： G11C11/5628 ,  G06N3/063 ,  G06N3/084

    摘要： Exemplary methods and apparatus are provided for implementing a deep learning accelerator (DLA) or other neural network components within the die of a non-volatile memory (NVM) apparatus using, for example, under-the-array circuit components within the die. Some aspects disclosed herein relate to configuring the under-the-array components to implement feedforward DLA operations. Other aspects relate to backpropagation operations. Still other aspects relate to using an NAND-based on-chip copy with update function to facilitate updating synaptic weights of a neural network stored on a die. Other aspects disclosed herein relate to configuring a solid state device (SSD) controller for use with the NVM. In some aspects, the SSD controller includes flash translation layer (FTL) tables configured specifically for use with neural network data stored in the NVM.

    Data integrity protection with partial updates
    8.
    发明授权
    Data integrity protection with partial updates 有权

    公开(公告)号：US11681581B1

    公开(公告)日：2023-06-20

    申请号：US17845770

    申请日：2022-06-21

    申请人： Western Digital Technologies, Inc.

    发明人： Ishai Ilani ,  Ran Zamir ,  Karin Inbar ,  Eran Sharon ,  Idan Alrod

    IPC分类号： G06F11/10 ,  G06F3/06

    CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/1004

    摘要： Effective use of cyclic redundancy check (CRC) signatures is achieved where each sector of a flash management unit (FMU) has a distinct CRC signature. The CRC signatures are XORed together to create a total CRC signature for the FMU. When a host device updates a single sector of the FMU, the CRC signature for the updated single sector can be changed by removing the old CRC signature corresponding to the single sector and replacing the old CRC signature with a new CRC signature corresponding to the updated single sector. The old CRC signature is XORed from the total CRC signature and then the new CRC signature is XORed with the remaining CRC signatures to create a new total CRC signature. In so doing, data integrity is ensured.