公开(公告)号：US20130033287A1

公开(公告)日：2013-02-07

申请号：US13197128

申请日：2011-08-03

申请人： Miao Li ,  Nam V. Dang ,  Xiaohua Kong

发明人： Miao Li ,  Nam V. Dang ,  Xiaohua Kong

IPC分类号： H03K19/003 ,  G06F17/50

CPC分类号： H03K19/018557 ,  H04L25/0278

摘要： A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor. The impedances of the first and second transistors may be controlled by the first gate control voltage and the second gate control voltage respectively.

摘要翻译： 公开了一种平衡的单端阻抗控制系统。 在特定实施例中，电路包括耦合到第一输出端的第一晶体管和耦合到第二输出端的第二晶体管。 电路还包括第三晶体管和第四晶体管，其中第三晶体管的器件特性基本上与第一晶体管的器件特性匹配，并且第四晶体管的器件特性基本上与第二晶体管的器件特性相匹配。 电路还包括第一控制路径和第二控制路径。 第一路径耦合到第三晶体管，并提供第一轨电压以控制第一晶体管的第一栅控制电压。 第二控制路径耦合到第四晶体管，并提供第二导轨电压以控制第二晶体管的第二栅极控制电压。 第一和第二晶体管的阻抗可以分别由第一栅极控制电压和第二栅极控制电压控制。

公开(公告)号：US20120177159A1

公开(公告)日：2012-07-12

申请号：US13005271

申请日：2011-01-12

申请人： Xiaohua Kong ,  Vannam Dang ,  Tirdad Sowlati

发明人： Xiaohua Kong ,  Vannam Dang ,  Tirdad Sowlati

IPC分类号： H04L7/02

CPC分类号： H04L7/033 ,  H03L7/07 ,  H03L7/0807 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0995

摘要： A bang-bang frequency detector with no data pattern dependency is provided. In examples, the detector recovers a clock from received data, such as data having a non-return to zero (NRZ) format. A first bang-bang phase detector (BBPD) provides first phase information about a phase difference between a sample clock and the clock embedded in the received data. A second BBPD provides second phase information about a second phase difference between the clock embedded in the received data and a delayed version of the sample clock. A frequency difference between the sample clock and the clock embedded in the received data is determined based on the first and second phase differences. The frequency difference can be used to adjust the frequency of the sample clock. A lock detector can be coupled to a BBPD output to determine if the sample clock is locked to the clock embedded in the received data.

摘要翻译： 提供了一种没有数据模式依赖性的爆轰频率检测器。 在示例中，检测器从接收的数据恢复时钟，例如具有不归零（NRZ）格式的数据。 第一个爆炸相位检测器（BBPD）提供关于采样时钟和嵌入在接收数据中的时钟之间的相位差的第一阶段信息。 第二BBPD提供关于嵌入在接收数据中的时钟与采样时钟的延迟版本之间的第二相位差的第二阶段信息。 基于第一和第二相位差来确定采样时钟和嵌入在接收数据中的时钟之间的频率差。 频率差可用于调整采样时钟的频率。 锁定检测器可以耦合到BBPD输出，以确定采样时钟是否锁定在嵌入在接收数据中的时钟。