公开(公告)号：US08630821B2

公开(公告)日：2014-01-14

申请号：US13189926

申请日：2011-07-25

申请人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

发明人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

IPC分类号： G06F11/30

CPC分类号： G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

摘要： System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

摘要翻译： 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

公开(公告)号：US20130120028A1

公开(公告)日：2013-05-16

申请号：US13294928

申请日：2011-11-11

申请人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang

发明人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03K3/00 ,  G06F19/00

CPC分类号： H03F1/223 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45085 ,  H03F3/45659 ,  H03F2203/45418 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03F2203/45726

摘要： A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.

摘要翻译： 具有共模连接的多端子输出包括具有第一端子和第二端子的输出端，并且在第一端子和第二端子之间具有共模连接。 晶体管的体连接耦合到共模连接。 产生第一组控制信号和第二组控制信号。 第一组控制信号中的每一个具有与第一功率域相关联的第一导轨电压电平。 第二组控制信号是从第一组控制信号产生的。 第二组控制信号中的每一个具有与第二功率域相关联的第二轨电压电平。 第二功率域与输出驱动器的输出的共模电压相关联。

公开(公告)号：US20130030767A1

公开(公告)日：2013-01-31

申请号：US13189926

申请日：2011-07-25

申请人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

发明人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang ,  Cheng Zhong

IPC分类号： G06F11/30

CPC分类号： G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

摘要： System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

摘要翻译： 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

公开(公告)号：US08890601B2

公开(公告)日：2014-11-18

申请号：US13294928

申请日：2011-11-11

申请人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang

发明人： Miao Li ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03B1/00 ,  H03F3/24 ,  H03F3/45 ,  H03F1/22 ,  H03F3/195

CPC分类号： H03F1/223 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45085 ,  H03F3/45659 ,  H03F2203/45418 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03F2203/45726

摘要： A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.

摘要翻译： 具有共模连接的多端子输出包括具有第一端子和第二端子的输出端，并且在第一端子和第二端子之间具有共模连接。 晶体管的体连接耦合到共模连接。 产生第一组控制信号和第二组控制信号。 第一组控制信号中的每一个具有与第一功率域相关联的第一导轨电压电平。 第二组控制信号是从第一组控制信号产生的。 第二组控制信号中的每一个具有与第二功率域相关联的第二轨电压电平。 第二功率域与输出驱动器的输出的共模电压相关联。

公开(公告)号：US20130120029A1

公开(公告)日：2013-05-16

申请号：US13294273

申请日：2011-11-11

申请人： Miao Li ,  Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

发明人： Miao Li ,  Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03K3/00

CPC分类号： H03K19/018514 ,  H04L25/0272 ,  H04L25/0286

摘要： In an example, a high-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications is provided. An exemplary integrated circuit includes a serializer, a pre-driver coupled to receive a differential input from the serializer, and a driver. The pre-driver includes all-p-type metal-oxide-silicon (PMOS) cross-coupled level converter comprising four PMOS transistors and two de-emphasis PMOS transistors forming a de-emphasis tap coupled to the output of the cross-coupled level converter. The driver is coupled to the pre-driver output and is configured to receive a differential input from the pre-driver.

摘要翻译： 在一个例子中，提供了一个高速预驱动器和电压电平转换器，内置去加重HDMI传输应用。 示例性集成电路包括串行器，耦合以从串行器接收差分输入的预驱动器和驱动器。 预驱动器包括全部p型金属氧化物硅（PMOS）交叉耦合电平转换器，其包括四个PMOS晶体管和两个去加重PMOS晶体管，其形成耦合到交叉耦合电平的输出的去加重抽头 转换器。 驱动器耦合到预驱动器输出，并被配置为从前驱动器接收差分输入。

公开(公告)号：US20130033287A1

公开(公告)日：2013-02-07

申请号：US13197128

申请日：2011-08-03

申请人： Miao Li ,  Nam V. Dang ,  Xiaohua Kong

发明人： Miao Li ,  Nam V. Dang ,  Xiaohua Kong

IPC分类号： H03K19/003 ,  G06F17/50

CPC分类号： H03K19/018557 ,  H04L25/0278

摘要： A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor. The impedances of the first and second transistors may be controlled by the first gate control voltage and the second gate control voltage respectively.

摘要翻译： 公开了一种平衡的单端阻抗控制系统。 在特定实施例中，电路包括耦合到第一输出端的第一晶体管和耦合到第二输出端的第二晶体管。 电路还包括第三晶体管和第四晶体管，其中第三晶体管的器件特性基本上与第一晶体管的器件特性匹配，并且第四晶体管的器件特性基本上与第二晶体管的器件特性相匹配。 电路还包括第一控制路径和第二控制路径。 第一路径耦合到第三晶体管，并提供第一轨电压以控制第一晶体管的第一栅控制电压。 第二控制路径耦合到第四晶体管，并提供第二导轨电压以控制第二晶体管的第二栅极控制电压。 第一和第二晶体管的阻抗可以分别由第一栅极控制电压和第二栅极控制电压控制。

公开(公告)号：US08618832B2

公开(公告)日：2013-12-31

申请号：US13197128

申请日：2011-08-03

申请人： Miao Li ,  Nam V. Dang ,  Xiaohua Kong

发明人： Miao Li ,  Nam V. Dang ,  Xiaohua Kong

IPC分类号： H03K19/003 ,  H03K19/0175

CPC分类号： H03K19/018557 ,  H04L25/0278

摘要： A balanced single-end impedance control system is disclosed. In a particular embodiment, the circuit includes a first transistor coupled to a first output terminal and a second transistor coupled to a second output terminal. The circuit also includes a third transistor and a fourth transistor, where device characteristics of the third transistor substantially match device characteristics of the first transistor and device characteristics of the fourth transistor substantially match device characteristics of the second transistor. The circuit further includes a first control path and a second control path. The first path is coupled to the third transistor and provides a first rail voltage to control a first gate control voltage of the first transistor. The second control path is coupled to the fourth transistor and provides a second rail voltage to control a second gate control voltage of the second transistor. The impedances of the first and second transistors may be controlled by the first gate control voltage and the second gate control voltage respectively.

摘要翻译： 公开了一种平衡的单端阻抗控制系统。 在特定实施例中，电路包括耦合到第一输出端的第一晶体管和耦合到第二输出端的第二晶体管。 电路还包括第三晶体管和第四晶体管，其中第三晶体管的器件特性基本上与第一晶体管的器件特性匹配，并且第四晶体管的器件特性基本上与第二晶体管的器件特性相匹配。 电路还包括第一控制路径和第二控制路径。 第一路径耦合到第三晶体管，并提供第一轨电压以控制第一晶体管的第一栅控制电压。 第二控制路径耦合到第四晶体管，并提供第二导轨电压以控制第二晶体管的第二栅极控制电压。 第一和第二晶体管的阻抗可以分别由第一栅极控制电压和第二栅极控制电压控制。

公开(公告)号：US08542039B2

公开(公告)日：2013-09-24

申请号：US13294273

申请日：2011-11-11

申请人： Miao Li ,  Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

发明人： Miao Li ,  Zhi Zhu ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H03K19/018514 ,  H04L25/0272 ,  H04L25/0286

摘要： In an example, a high-speed pre-driver and voltage level converter with built-in de-emphasis for HDMI transmit applications is provided. An exemplary integrated circuit includes a serializer, a pre-driver coupled to receive a differential input from the serializer, and a driver. The pre-driver includes all-p-type metal-oxide-silicon (PMOS) cross-coupled level converter comprising four PMOS transistors and two de-emphasis PMOS transistors forming a de-emphasis tap coupled to the output of the cross-coupled level converter. The driver is coupled to the pre-driver output and is configured to receive a differential input from the pre-driver.

摘要翻译： 在一个例子中，提供了一个高速预驱动器和电压电平转换器，内置去加重HDMI传输应用。 示例性集成电路包括串行器，耦合以从串行器接收差分输入的预驱动器和驱动器。 预驱动器包括全部p型金属氧化物硅（PMOS）交叉耦合电平转换器，其包括四个PMOS晶体管和两个去加重PMOS晶体管，其形成耦合到交叉耦合电平的输出的去加重抽头 转换器。 驱动器耦合到预驱动器输出，并被配置为从前驱动器接收差分输入。

公开(公告)号：US20130120020A1

公开(公告)日：2013-05-16

申请号：US13294482

申请日：2011-11-11

申请人： Miao Li ,  Behnam Amelifard ,  Xiaohua Kong ,  Nam V. Dang

发明人： Miao Li ,  Behnam Amelifard ,  Xiaohua Kong ,  Nam V. Dang

IPC分类号： H03K19/003

CPC分类号： H03K19/018564 ,  H03K19/01855 ,  H04L25/0264

摘要： An adjustable gain line driver receives an input signal and a gain control signal and outputs a signal with a swing, and the swing is measured to generate a swing measurement signal. A target swing signal is generated having a target swing, and the target swing signal is measured to generate a target swing reference signal. The swing measurement signal is compared to the target swing reference control signal and a counter generating the gain control signal is incremented until the measurement signal meets the target swing reference signal. Optionally a reset signal resets the counter, and the gain control signal, at predetermined events.

摘要翻译： 可调增益线驱动器接收输入信号和增益控制信号并输出​​具有摆幅的信号，并且测量摆动以产生摆动测量信号。 产生具有目标摆动的目标摆动信号，并且测量目标摆动信号以产生目标摆动参考信号。 将摆动测量信号与目标摆动参考控制信号进行比较，生成增益控制信号的计数器递增，直到测量信号满足目标摆动参考信号为止。 可选地，复位信号在预定事件时复位计数器和增益控制信号。

公开(公告)号：US08837310B2

公开(公告)日：2014-09-16

申请号：US13259312

申请日：2010-03-24

申请人： Dafei Wang ,  Delong Tang ,  Xiaoan Hou ,  Miao Li

发明人： Dafei Wang ,  Delong Tang ,  Xiaoan Hou ,  Miao Li

IPC分类号： H04W36/02 ,  H04W28/10 ,  H04L12/801 ,  H04J3/06 ,  H04W28/14 ,  H04W24/00 ,  H04W92/04

CPC分类号： H04W24/00 ,  H04J3/06 ,  H04L47/34 ,  H04W28/10 ,  H04W28/14 ,  H04W36/02 ,  H04W92/045

摘要： The invention provides a method and a system for determining an end time of uplink back propagation in a mobile communication system to solve a problem of accurately judging the end time of uplink back propagation, wherein the method includes the following steps: sending data with consecutive sequence numbers in a buffer of a packet data convergence protocol (PDCP) module to a serving gateway (S-GW) via an S1 tunnel; sending data with inconsecutive sequence numbers, which is from data with a first inconsecutive sequence number to last data in the buffer of the PDCP module, to a target base station via an uplink back propagation tunnel; generating an end marker datagram; sending the end marker datagram to the target base station via the uplink back propagation tunnel; and receiving, by the target base station, the end marker datagram and determining that the uplink back propagation has ended.

摘要翻译： 本发明提供了一种用于确定移动通信系统中上行反向传播的结束时间的方法和系统，以解决精确地判断上行反向传播的结束时间的问题，其中该方法包括以下步骤：以连续序列发送数据 分组数据汇聚协议（PDCP）模块的缓冲器中的号码经由S1隧道传送到服务网关（S-GW）; 将来自具有第一不连续序列号的数据的数据与PDCP模块的缓冲器中的最后数据经由上行链路反向传播隧道发送到目标基站的序列号不一致的数据; 生成结束标记数据报; 通过上行链路反向传播隧道将终端标记数据报发送到目标基站; 并且由目标基站接收终端标记数据报，并确定上行链路反向传播已经结束。