公开(公告)号：US06236117B1

公开(公告)日：2001-05-22

申请号：US09048066

申请日：1998-03-26

申请人： Yoshiyuki Ishigaki ,  Hiroki Honda

发明人： Yoshiyuki Ishigaki ,  Hiroki Honda

IPC分类号： H01L2711

CPC分类号： H01L27/11 ,  H01L27/1112 ,  Y10S257/904

摘要： A semiconductor device including a shunt interconnection which operates at higher speed and permits high density integration is provided. In the semiconductor device including the shunt interconnection, a shunt connection region for a word line and a first shunt interconnection including a metal are formed in the memory cell region. In the memory cell region, shunt connection region and shunt interconnection are electrically connected with each other through a word line contact plug formed in a contact hole.

摘要翻译： 提供了包括以更高速度操作并且允许高密度集成的并联互连的半导体器件。 在包括并联互连的半导体器件中，在存储单元区域中形成用于字线的分流连接区域和包括金属的第一分路互连。 在存储单元区域中，分流连接区域和并联互连通过形成在接触孔中的字线接触插塞彼此电连接。

公开(公告)号：US06198149B1

公开(公告)日：2001-03-06

申请号：US08850839

申请日：1997-05-02

申请人： Yoshiyuki Ishigaki

发明人： Yoshiyuki Ishigaki

IPC分类号： H01L2354

CPC分类号： H01L23/544 ,  H01L21/76801 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/5258 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on the element forming region and extended over the element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under the gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near the gate electrode on the second impurity region. In this semiconductor device, a distance defined from an outer edge of the gate electrode on the side of the first impurity region to another outer edge of the first insulating film on the side apart from the gate electrode is longer than a distance defined from an outer edge of the gate electrode on the side of the second impurity region to another outer edge of the second insulating film on the side apart from the gate electrode.

摘要翻译： 半导体器件包括：形成在半导体衬底的一个主表面上的元件隔离膜; 元件形成区域，形成在主表面上并被元件隔离膜包围; 通过元件形成区上的栅极绝缘膜形成并在元件隔离膜上延伸的栅电极; 形成在元件形成区域中的第一和第二杂质区域从半导体衬底的表面露出的部分与元件隔离膜接触并且在栅电极下方彼此相对定位; 第一绝缘膜，形成在第一杂质区域上的栅电极附近，并且在元件隔离膜内延伸到栅极上并靠近栅电极的延伸部分; 以及形成在第二杂质区域上的栅电极附近的第二绝缘膜。 在该半导体器件中，从第一杂质区域侧的栅电极的外边缘到与栅电极相离的一侧的第一绝缘膜的另一外缘限定的距离比从外部限定的距离长 在第二杂质区一侧的栅电极的边缘与第二绝缘膜的与栅电极分开的一侧的另一外边缘。

公开(公告)号：US5994719A

公开(公告)日：1999-11-30

申请号：US116245

申请日：1998-07-16

申请人： Hirotada Kuriyama ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

发明人： Hirotada Kuriyama ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

IPC分类号： H01L27/11 ,  H01L21/8244 ,  H01L29/76

CPC分类号： H01L27/1108 ,  H01L27/11 ,  Y10S257/903

摘要： The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

摘要翻译： 本发明提供一种改进的静态随机存取存储器，其可以被制造成通过光刻设计的值。 在第一存储单元和第二存储单元之间的边界处提供用于连接用于第一和第二存储单元的有源区和接地线的第二直接合同。 第二直接接触被分成多个部分。

公开(公告)号：US5777920A

公开(公告)日：1998-07-07

申请号：US648605

申请日：1996-05-15

申请人： Yoshiyuki Ishigaki ,  Kazuhito Tsutsumi

发明人： Yoshiyuki Ishigaki ,  Kazuhito Tsutsumi

IPC分类号： H01L21/336 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/10 ,  H01L27/11 ,  H01L29/78 ,  G11C11/00

CPC分类号： H01L27/0629 ,  H01L27/11 ,  Y10S257/903

摘要： A groove is formed at a surface of a p.sup.- -well region. One of source/drain regions of each of access transistors has an n.sup.- -impurity region and an n.sup.+ -impurity region forming an LDD structure. Another n.sup.- -impurity region is disposed such that n.sup.+ -impurity region is located between these n.sup.- -impurity regions, and is formed at the whole bottom surface of groove. Thereby, it is possible to provide a semiconductor memory device of a high performance including an SRAM in which resistance against soft error is improved, a junction leak current is reduced and a current consumption during standby can be reduced.

摘要翻译： 在p阱区域的表面上形成凹槽。 每个存取晶体管的源极/漏极区之一具有形成LDD结构的n - 杂质区和n + - 纯度区。 设置另一个n - 杂质区，使得n +极性区域位于这些n-杂质区之间，并且形成在凹槽的整个底表面。 由此，可以提供一种高性能的半导体存储器件，其包括其中提高了抗软性电阻的电阻，减少了结漏电流并且可以减少待机期间的电流消耗的SRAM。

公开(公告)号：US5471085A

公开(公告)日：1995-11-28

申请号：US310526

申请日：1994-09-22

申请人： Yoshiyuki Ishigaki ,  Hiroki Honda ,  Kimiharu Uga ,  Masahiro Ishida

发明人： Yoshiyuki Ishigaki ,  Hiroki Honda ,  Kimiharu Uga ,  Masahiro Ishida

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417 ,  H01L29/732 ,  H01L29/72

CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/41708

摘要： An n.sup.+ buried layer is formed on a surface of p.sup.- semiconductor substrate. An n.sup.- epitaxial growth layer and an n.sup.+ diffusion layer are formed on a surface of n.sup.+ buried layer. A p.sup.- base region and p.sup.+ external base region adjoining to each other are formed on a surface of n.sup.- epitaxial growth layer. An an n.sup.+ emitter region is formed at a surface of p.sup.- base region. An emitter electrode is formed adjacently to n.sup.+ emitter region. The emitter electrode is made of polycrystalline silicon doped with phosphorus at a concentration from 1.times.10.sup.20 cm.sup.-3 to 6.times.10.sup.20 cm.sup.-3.

摘要翻译： 在p-半导体衬底的表面上形成n +掩埋层。 在n +掩埋层的表面上形成n外延生长层和n +扩散层。 在n-外延生长层的表面上形成彼此相邻的p-基区和p +外基区。 在p基极区的表面形成n +射极区。 发射极电极与n +发射极区域相邻形成。 发射电极由掺杂浓度为1×10 20 cm -3至6×10 20 cm -3的磷的多晶硅制成。

公开(公告)号：US5319234A

公开(公告)日：1994-06-07

申请号：US916666

申请日：1992-07-22

申请人： Kimiharu Uga ,  Hiroki Honda ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

发明人： Kimiharu Uga ,  Hiroki Honda ,  Masahiro Ishida ,  Yoshiyuki Ishigaki

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L27/02

CPC分类号： H01L27/0623

摘要： There is disclosed a C-BiCMOS semiconductor device in which a base electrode (300) of an NPN bipolar transistor and a drain electrode (360) of a PMOS transistor are formed of the same polycrystalline semiconductor, in which a base electrode (310) of a PNP bipolar transistor and a drain electrode (350) of an NMOS transistor are formed of the same polycrystalline semiconductor, and in which a source electrode (530) of the PMOS transistor and a source electrode (520) of the NMOS transistor are formed of aluminium wiring. The C-BiCMOS semiconductor device achieves preferable electric conductivity in the source electrodes, size reduction in the drain electrodes, and simplified process steps in the formation of the base electrodes of the bipolar transistors, so that the size of the devices is reduced in simple process steps without deterioration of the electric conductivity.

摘要翻译： 公开了一种C-BiCMOS半导体器件，其中NPN双极晶体管的基极（300）和PMOS晶体管的漏电极（360）由相同的多晶半导体形成，其中基极（310）为 NMOS晶体管的PNP双极晶体管和漏电极（350）由相同的多晶半导体形成，其中PMOS晶体管的源电极（530）和NMOS晶体管的源电极（520）由 铝接线。 C-BiCMOS半导体器件在源电极中实现优选的导电性，漏电极的尺寸减小，以及双极晶体管的基极形成中的简化工艺步骤，从而在简单的工艺中减小器件的尺寸 步骤不劣化导电性。